From patchwork Mon Apr 4 11:02:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navin P.S" X-Patchwork-Id: 605839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qdpwk3wWVz9s9n for ; Mon, 4 Apr 2016 21:02:30 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=HdTSZGW9; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753436AbcDDLC3 (ORCPT ); Mon, 4 Apr 2016 07:02:29 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:35348 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753374AbcDDLC2 (ORCPT ); Mon, 4 Apr 2016 07:02:28 -0400 Received: by mail-pa0-f54.google.com with SMTP id td3so141907889pab.2 for ; Mon, 04 Apr 2016 04:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:subject:message-id:mime-version:content-disposition :user-agent; bh=1luaB0YIJoIiM2PWSGjcysReIBUMiKwa1rzBxXxOI1Q=; b=HdTSZGW9ZDce53+YIBJEqxVao93r/FTRl64nwMGOksvHRg+TYL0TdVB7ReFejFEH5Y RHnDsMeIsX5yQN1bQ1DMCaQjVA1lzRS0y7W6FucGh36a++5KPsaXYP11VJKsWA+KQeJj QYdtIHLVbA7jYSP4pCi/ri4u96wsJ3TX/FN7aNIvVXSc+G3qBSHEAtNF2tC9g9iYxY53 mVzPbMLD+sSrbP6VL1O+0PbDxBMRUZ9Dtj98zLFvnHjCet0OK3UfWVXGsO15SWRIPvOY AwsGBD99R7VhIEXmxg3zQgEOv3vizd0Mt/WmYoBQY/ynRABsxNwndRR+3jRlj1/XH4Uq xToQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:subject:message-id:mime-version :content-disposition:user-agent; bh=1luaB0YIJoIiM2PWSGjcysReIBUMiKwa1rzBxXxOI1Q=; b=Oo9K234/UTBUHdaM3HGYnHfztjuSTDmqZLuefUJFabWyuo1zNFUEZm7JQXAFXB0lNC IEZmRecMMner3nXnzyDSDwGaz4Y6wRnocqMftuwydBCZW9T8Aw29SCDPFAwt3d3m8Anz Ii8vk0LUxxAHSPzeZ71Gi59jMJnTdin1K2G8zkb9RcbwP+wBkAHaWzdy2HePExIANR32 wWj1jRVuQfKj4cF6b98qYw8wq9AhehrCVL6//RRccpDclp33RCMpXDW3sHJeLNBfwdi+ Ebnp7xoh6uGJ6sMd+bByfHk2GhHVm7EiM4cs7M/jzWOPQNpAPfLbnX6ILOCrBeasDLab M9tQ== X-Gm-Message-State: AD7BkJLbSiePZxtM8UzUeffXacvAtDOY6JpuHEdNF2Gxm3kgHUWoQc4rkGLNxolPFhdhYw== X-Received: by 10.66.193.202 with SMTP id hq10mr51140457pac.6.1459767747860; Mon, 04 Apr 2016 04:02:27 -0700 (PDT) Received: from junk-foo ([103.227.96.224]) by smtp.gmail.com with ESMTPSA id dy6sm40840437pab.48.2016.04.04.04.02.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Apr 2016 04:02:27 -0700 (PDT) Date: Mon, 4 Apr 2016 16:32:23 +0530 From: "Navin P.S" To: linux-gpio@vger.kernel.org Subject: [ PATCH ] Bug 114711 - ubsan: "shift exponent 32 is too large" nouveau/nvkm/subdev/gpio/base.c:167:16 Message-ID: <20160404110222.GA8011@junk-foo> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi, Please find the below patch that fixes "Bug 114711 - ubsan: "shift exponent 32 is too large" in drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c:167:16" At runtime we shift 1 by 32 which is not correct since 1 is a signed integer. I make it unsigned and the maximum we shift is 32. --- drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index d45ec99..cd28376 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -164,7 +164,7 @@ static int nvkm_gpio_fini(struct nvkm_subdev *subdev, bool suspend) { struct nvkm_gpio *gpio = nvkm_gpio(subdev); - u32 mask = (1 << gpio->func->lines) - 1; + u32 mask = (1U << (min(gpio->func->lines, 32))) - 1; gpio->func->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0); gpio->func->intr_stat(gpio, &mask, &mask);