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[v2,6/8] target-mips: check CP0 enabled for CACHE instruction also in R6

Message ID 1458913777-28034-7-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae March 25, 2016, 1:49 p.m. UTC 
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@  static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC: