| Message ID | 1458763968-829-2-git-send-email-york.sun@nxp.com |
|---|---|
| State | Superseded |
| Headers | show |
> -----Original Message----- > From: York Sun [mailto:york.sun@nxp.com] > Sent: Thursday, March 24, 2016 1:43 AM > To: U-Boot Mailing List <u-boot@lists.denx.de> > Cc: Stuart Yoder <stuart.yoder@nxp.com>; Scott Wood <oss@buserror.net>; > Huan Wang <alison.wang@nxp.com>; york sun <york.sun@nxp.com>; > Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Ramneek Mehresh > <ramneek.mehresh@freescale.com>; Pratiyush Mohan Srivastava > <pratiyush.srivastava@freescale.com>; Li Yang <leoli@freescale.com>; Hou > Zhiqiang <B48286@freescale.com>; Shaohui Xie > <Shaohui.Xie@freescale.com>; Aneesh Bansal <aneesh.bansal@nxp.com>; > Jaiprakash Singh <b44839@freescale.com>; Mingkai Hu > <Mingkai.Hu@freescale.com>; Haiying Wang > <Haiying.Wang@freescale.com>; Albert Aribaud > <albert.u.boot@aribaud.net>; Minghuan Lian > <Minghuan.Lian@freescale.com>; Alexander Graf <agraf@suse.de>; Lijun > Pan <Lijun.Pan@freescale.com>; Scott Wood <scottwood@freescale.com>; > Gong Qianyu <Qianyu.Gong@freescale.com>; Joe Hershberger > <joe.hershberger@ni.com>; Prabhakar Kushwaha > <prabhakar@freescale.com>; Simon Glass <sjg@chromium.org>; Shengzhou > Liu <shengzhou.liu@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Bhupesh > Sharma <bhupesh.sharma@freescale.com>; Qianyu Gong > <qianyu.gong@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Thomas > Chou <thomas@wytron.com.tw>; Tang Yuantian > <Yuantian.Tang@freescale.com>; Alison Wang <b18965@freescale.com> > Subject: [RFC PATCH v1] armv8: LS2080A: Consolidate LS2080A and LS2085A > > LS2080A is the primary SoC, and LS2085A is a personality with AIOP > and DPAA DDR. The RDB and QDS boards support both personality. By > detecting the SVR at runtime, a single image per board can support > both SoCs. It gives users flexibility to swtich SoC without the need > to reprogram the board. > > Signed-off-by: York Sun <york.sun@nxp.com> > CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > > --- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 --- > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++--- > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 ++++- > arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 14 +++++++++- > arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 +-- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++----- > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++ > board/freescale/ls2080a/ddr.c | 27 +++++++++++--------- > board/freescale/ls2080a/ls2080a.c | 2 +- > board/freescale/ls2080aqds/MAINTAINERS | 2 -- > board/freescale/ls2080aqds/ddr.c | 27 +++++++++++--------- > board/freescale/ls2080aqds/ls2080aqds.c | 2 +- > board/freescale/ls2080ardb/MAINTAINERS | 2 -- > board/freescale/ls2080ardb/ddr.c | 27 +++++++++++--------- > board/freescale/ls2080ardb/ls2080ardb.c | 2 +- > configs/ls2085aqds_defconfig | 19 -------------- > configs/ls2085aqds_nand_defconfig | 14 ---------- > configs/ls2085ardb_defconfig | 19 -------------- > configs/ls2085ardb_nand_defconfig | 14 ---------- > drivers/net/ldpaa_eth/Makefile | 1 - > include/configs/ls2080a_common.h | 7 +---- > include/configs/ls2080a_emu.h | 7 ----- > include/configs/ls2080a_simu.h | 7 ----- > include/linux/usb/xhci-fsl.h | 2 +- > 27 files changed, 83 insertions(+), 152 deletions(-) > delete mode 100644 configs/ls2085aqds_defconfig > delete mode 100644 configs/ls2085aqds_nand_defconfig > delete mode 100644 configs/ls2085ardb_defconfig > delete mode 100644 configs/ls2085ardb_nand_defconfig > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > index cce7405..5f86ef9 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > @@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),) > obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o > endif > > -ifneq ($(CONFIG_LS2085A),) > -obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o > -endif > - > ifneq ($(CONFIG_LS1043A),) > obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o > endif > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > index 4b9e209..d939900 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > @@ -538,12 +538,12 @@ int print_cpuinfo(void) > struct sys_info sysinfo; > char buf[32]; > unsigned int i, core; > - u32 type, rcw; > + u32 type, rcw, svr = gur_in32(&gur->svr); > > puts("SoC: "); > > cpu_name(buf); > - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); > + printf(" %s (0x%x)\n", buf, svr); > memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); > get_sys_info(&sysinfo); > puts("Clock Configuration:"); > @@ -564,7 +564,10 @@ int print_cpuinfo(void) > printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); > #endif > #ifdef CONFIG_SYS_FSL_HAS_DP_DDR > - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); > + if (soc_has_dp_ddr()) { If new function soc_has_dp_ddr() is being used then CONFIG_SYS_FSL_HAS_DP_DDR should be removed. > + printf(" DP-DDR: %-4s MT/s", > + strmhz(buf, sysinfo.freq_ddrbus2)); > + } > #endif > puts("\n"); > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > index 81cf470..d580a43 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > @@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info) > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > #ifdef CONFIG_SYS_FSL_HAS_DP_DDR > - sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> > + if (soc_has_dp_ddr()) { If new function soc_has_dp_ddr() is being used then CONFIG_SYS_FSL_HAS_DP_DDR should be removed. > + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> > FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & > FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; > + } else { > + sys_info->freq_ddrbus2 = 0; > + } > #endif > > for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > index 9c69ed1..04831ca 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > @@ -20,7 +20,7 @@ ENTRY(lowlevel_init) > #ifdef CONFIG_FSL_LSCH3 > > /* Set Wuo bit for RN-I 20 */ > -#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) > +#ifdef CONFIG_LS2080A > ldr x0, =CCI_AUX_CONTROL_BASE(20) > ldr x1, =0x00000010 > bl ccn504_set_aux > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index 213ce3a..d609d81 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > @@ -18,7 +18,19 @@ > > DECLARE_GLOBAL_DATA_PTR; > > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +bool soc_has_dp_ddr(void) > +{ > + struct ccsr_gur __iomem *gur = (void > *)(CONFIG_SYS_FSL_GUTS_ADDR); > + u32 svr = gur_in32(&gur->svr); > + > + /* LS2085A has DP_DDR */ > + if (SVR_SOC_VER(svr) == SVR_LS2085) > + return true; > + > + return false; > +} > + > +#ifdef CONFIG_LS2080A > /* > * This erratum requires setting a value to eddrtqcr1 to > * optimal the DDR performance. > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c > b/arch/arm/cpu/armv8/fsl-layerscape/spl.c > index f434c44..c1229c8 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c > @@ -46,7 +46,7 @@ void board_init_f(ulong dummy) > { > /* Clear global data */ > memset((void *)gd, 0, sizeof(gd_t)); > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +#ifdef CONFIG_LS2080A Why cannot this config be removed? It looks to be part of generic flow and can be used in future Layerscape SoCs. > arch_cpu_init(); > #endif > #ifdef CONFIG_FSL_IFC > @@ -54,7 +54,7 @@ void board_init_f(ulong dummy) > #endif > board_early_init_f(); > timer_init(); > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +#ifdef CONFIG_LS2080A Same as above > env_init(); > #endif > get_clocks(); > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index bfaece2..6ca4bc2 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -23,16 +23,11 @@ > */ > #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* > 2MB */ > > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +#ifdef CONFIG_LS2080A > #define CONFIG_MAX_CPUS 16 > #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 > -#ifdef CONFIG_LS2080A > -#define CONFIG_NUM_DDR_CONTROLLERS 2 > -#endif > -#ifdef CONFIG_LS2085A > #define CONFIG_NUM_DDR_CONTROLLERS 3 > -#define CONFIG_SYS_FSL_HAS_DP_DDR > -#endif > +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to > confirm */ > #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } > #define SRDS_MAX_LANES 8 > #define CONFIG_SYS_FSL_SRDS_1 > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h > b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h > index 93bbda3..71c428f 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h > @@ -203,7 +203,7 @@ static const struct sys_mmu_table final_mmu_table[] > = { > { CONFIG_SYS_PCIE3_PHYS_ADDR, > CONFIG_SYS_PCIE3_PHYS_ADDR, > CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, > PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +#ifdef CONFIG_LS2080A I will propose to use #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR > { CONFIG_SYS_PCIE4_PHYS_ADDR, > CONFIG_SYS_PCIE4_PHYS_ADDR, > CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, > PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > index d1fbde7..f71c2c1 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > @@ -9,7 +9,7 @@ > > #include <config.h> > > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +#ifdef CONFIG_LS2080A Use CONFIG_FSL_LSCH3, as it will be used future SOCs also. > enum srds_prtcl { > NONE = 0, > PCIE1, > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > index ea78e15..0916897 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > @@ -93,4 +93,6 @@ void cpu_name(char *name); > #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 > void erratum_a009635(void); > #endif <snip> > @@ -7,4 +7,3 @@ > obj-y += ldpaa_wriop.o > obj-y += ldpaa_eth.o > obj-$(CONFIG_LS2080A) += ls2080a.o > -obj-$(CONFIG_LS2085A) += ls2080a.o > diff --git a/include/configs/ls2080a_common.h > b/include/configs/ls2080a_common.h > index 13ce349..57e2a29 100644 > --- a/include/configs/ls2080a_common.h > +++ b/include/configs/ls2080a_common.h > @@ -171,10 +171,9 @@ unsigned long long get_qixis_addr(void); > #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 > #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 > #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 > -#ifdef CONFIG_LS2085A > +/* For LS2085A */ > #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 > #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 > -#endif CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET --> permanent enabled. LS2080A (NON-AIOP) personality may execute AIOP code code in driver/net/fsl-mc/mc.c. Need to put under svr check. --prabhakar
On 03/26/2016 03:39 AM, Prabhakar Kushwaha wrote: > >> -----Original Message----- >> From: York Sun [mailto:york.sun@nxp.com] >> Sent: Thursday, March 24, 2016 1:43 AM >> To: U-Boot Mailing List <u-boot@lists.denx.de> >> Cc: Stuart Yoder <stuart.yoder@nxp.com>; Scott Wood <oss@buserror.net>; >> Huan Wang <alison.wang@nxp.com>; york sun <york.sun@nxp.com>; >> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Ramneek Mehresh >> <ramneek.mehresh@freescale.com>; Pratiyush Mohan Srivastava >> <pratiyush.srivastava@freescale.com>; Li Yang <leoli@freescale.com>; Hou >> Zhiqiang <B48286@freescale.com>; Shaohui Xie >> <Shaohui.Xie@freescale.com>; Aneesh Bansal <aneesh.bansal@nxp.com>; >> Jaiprakash Singh <b44839@freescale.com>; Mingkai Hu >> <Mingkai.Hu@freescale.com>; Haiying Wang >> <Haiying.Wang@freescale.com>; Albert Aribaud >> <albert.u.boot@aribaud.net>; Minghuan Lian >> <Minghuan.Lian@freescale.com>; Alexander Graf <agraf@suse.de>; Lijun >> Pan <Lijun.Pan@freescale.com>; Scott Wood <scottwood@freescale.com>; >> Gong Qianyu <Qianyu.Gong@freescale.com>; Joe Hershberger >> <joe.hershberger@ni.com>; Prabhakar Kushwaha >> <prabhakar@freescale.com>; Simon Glass <sjg@chromium.org>; Shengzhou >> Liu <shengzhou.liu@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Bhupesh >> Sharma <bhupesh.sharma@freescale.com>; Qianyu Gong >> <qianyu.gong@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Thomas >> Chou <thomas@wytron.com.tw>; Tang Yuantian >> <Yuantian.Tang@freescale.com>; Alison Wang <b18965@freescale.com> >> Subject: [RFC PATCH v1] armv8: LS2080A: Consolidate LS2080A and LS2085A >> >> LS2080A is the primary SoC, and LS2085A is a personality with AIOP >> and DPAA DDR. The RDB and QDS boards support both personality. By >> detecting the SVR at runtime, a single image per board can support >> both SoCs. It gives users flexibility to swtich SoC without the need >> to reprogram the board. >> >> Signed-off-by: York Sun <york.sun@nxp.com> >> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> >> >> --- >> >> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 --- >> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++--- >> .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 ++++- >> arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 14 +++++++++- >> arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 +-- >> arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++----- >> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- >> .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- >> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++ >> board/freescale/ls2080a/ddr.c | 27 +++++++++++--------- >> board/freescale/ls2080a/ls2080a.c | 2 +- >> board/freescale/ls2080aqds/MAINTAINERS | 2 -- >> board/freescale/ls2080aqds/ddr.c | 27 +++++++++++--------- >> board/freescale/ls2080aqds/ls2080aqds.c | 2 +- >> board/freescale/ls2080ardb/MAINTAINERS | 2 -- >> board/freescale/ls2080ardb/ddr.c | 27 +++++++++++--------- >> board/freescale/ls2080ardb/ls2080ardb.c | 2 +- >> configs/ls2085aqds_defconfig | 19 -------------- >> configs/ls2085aqds_nand_defconfig | 14 ---------- >> configs/ls2085ardb_defconfig | 19 -------------- >> configs/ls2085ardb_nand_defconfig | 14 ---------- >> drivers/net/ldpaa_eth/Makefile | 1 - >> include/configs/ls2080a_common.h | 7 +---- >> include/configs/ls2080a_emu.h | 7 ----- >> include/configs/ls2080a_simu.h | 7 ----- >> include/linux/usb/xhci-fsl.h | 2 +- >> 27 files changed, 83 insertions(+), 152 deletions(-) >> delete mode 100644 configs/ls2085aqds_defconfig >> delete mode 100644 configs/ls2085aqds_nand_defconfig >> delete mode 100644 configs/ls2085ardb_defconfig >> delete mode 100644 configs/ls2085ardb_nand_defconfig >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> index cce7405..5f86ef9 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> @@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),) >> obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o >> endif >> >> -ifneq ($(CONFIG_LS2085A),) >> -obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o >> -endif >> - >> ifneq ($(CONFIG_LS1043A),) >> obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o >> endif >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> index 4b9e209..d939900 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c >> @@ -538,12 +538,12 @@ int print_cpuinfo(void) >> struct sys_info sysinfo; >> char buf[32]; >> unsigned int i, core; >> - u32 type, rcw; >> + u32 type, rcw, svr = gur_in32(&gur->svr); >> >> puts("SoC: "); >> >> cpu_name(buf); >> - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); >> + printf(" %s (0x%x)\n", buf, svr); >> memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); >> get_sys_info(&sysinfo); >> puts("Clock Configuration:"); >> @@ -564,7 +564,10 @@ int print_cpuinfo(void) >> printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); >> #endif >> #ifdef CONFIG_SYS_FSL_HAS_DP_DDR >> - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); >> + if (soc_has_dp_ddr()) { > > If new function soc_has_dp_ddr() is being used then CONFIG_SYS_FSL_HAS_DP_DDR should be removed. I am not strongly against the idea to remove CONFIG_SYS_FSL_HAS_DP_DDR. But given the number of SoCs with DP_DDR, keeping this macro can reduce the image size for other SoCs. > > >> + printf(" DP-DDR: %-4s MT/s", >> + strmhz(buf, sysinfo.freq_ddrbus2)); >> + } >> #endif >> puts("\n"); >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >> index 81cf470..d580a43 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >> @@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; >> #ifdef CONFIG_SYS_FSL_HAS_DP_DDR >> - sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> >> + if (soc_has_dp_ddr()) { > > If new function soc_has_dp_ddr() is being used then CONFIG_SYS_FSL_HAS_DP_DDR should be removed. > >> + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; >> + } else { >> + sys_info->freq_ddrbus2 = 0; >> + } >> #endif >> >> for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S >> b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S >> index 9c69ed1..04831ca 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S >> @@ -20,7 +20,7 @@ ENTRY(lowlevel_init) >> #ifdef CONFIG_FSL_LSCH3 >> >> /* Set Wuo bit for RN-I 20 */ >> -#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) >> +#ifdef CONFIG_LS2080A >> ldr x0, =CCI_AUX_CONTROL_BASE(20) >> ldr x1, =0x00000010 >> bl ccn504_set_aux >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> index 213ce3a..d609d81 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> @@ -18,7 +18,19 @@ >> >> DECLARE_GLOBAL_DATA_PTR; >> >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +bool soc_has_dp_ddr(void) >> +{ >> + struct ccsr_gur __iomem *gur = (void >> *)(CONFIG_SYS_FSL_GUTS_ADDR); >> + u32 svr = gur_in32(&gur->svr); >> + >> + /* LS2085A has DP_DDR */ >> + if (SVR_SOC_VER(svr) == SVR_LS2085) >> + return true; >> + >> + return false; >> +} >> + >> +#ifdef CONFIG_LS2080A >> /* >> * This erratum requires setting a value to eddrtqcr1 to >> * optimal the DDR performance. >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c >> b/arch/arm/cpu/armv8/fsl-layerscape/spl.c >> index f434c44..c1229c8 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c >> @@ -46,7 +46,7 @@ void board_init_f(ulong dummy) >> { >> /* Clear global data */ >> memset((void *)gd, 0, sizeof(gd_t)); >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +#ifdef CONFIG_LS2080A > > Why cannot this config be removed? > It looks to be part of generic flow and can be used in future Layerscape SoCs. It is not in the scope of this patch. > >> arch_cpu_init(); >> #endif >> #ifdef CONFIG_FSL_IFC >> @@ -54,7 +54,7 @@ void board_init_f(ulong dummy) >> #endif >> board_early_init_f(); >> timer_init(); >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +#ifdef CONFIG_LS2080A > > Same as above > >> env_init(); >> #endif >> get_clocks(); >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h >> b/arch/arm/include/asm/arch-fsl-layerscape/config.h >> index bfaece2..6ca4bc2 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h >> @@ -23,16 +23,11 @@ >> */ >> #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* >> 2MB */ >> >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +#ifdef CONFIG_LS2080A >> #define CONFIG_MAX_CPUS 16 >> #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 >> -#ifdef CONFIG_LS2080A >> -#define CONFIG_NUM_DDR_CONTROLLERS 2 >> -#endif >> -#ifdef CONFIG_LS2085A >> #define CONFIG_NUM_DDR_CONTROLLERS 3 >> -#define CONFIG_SYS_FSL_HAS_DP_DDR >> -#endif >> +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to >> confirm */ >> #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } >> #define SRDS_MAX_LANES 8 >> #define CONFIG_SYS_FSL_SRDS_1 >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >> b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >> index 93bbda3..71c428f 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h >> @@ -203,7 +203,7 @@ static const struct sys_mmu_table final_mmu_table[] >> = { >> { CONFIG_SYS_PCIE3_PHYS_ADDR, >> CONFIG_SYS_PCIE3_PHYS_ADDR, >> CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, >> PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +#ifdef CONFIG_LS2080A > > I will propose to use #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR Yes, you can. It is not in the scope of this patch. > >> { CONFIG_SYS_PCIE4_PHYS_ADDR, >> CONFIG_SYS_PCIE4_PHYS_ADDR, >> CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, >> PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h >> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h >> index d1fbde7..f71c2c1 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h >> @@ -9,7 +9,7 @@ >> >> #include <config.h> >> >> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) >> +#ifdef CONFIG_LS2080A > > Use CONFIG_FSL_LSCH3, as it will be used future SOCs also. Same reason here. > >> enum srds_prtcl { >> NONE = 0, >> PCIE1, >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h >> b/arch/arm/include/asm/arch-fsl-layerscape/soc.h >> index ea78e15..0916897 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h >> @@ -93,4 +93,6 @@ void cpu_name(char *name); >> #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 >> void erratum_a009635(void); >> #endif > > <snip> > >> @@ -7,4 +7,3 @@ >> obj-y += ldpaa_wriop.o >> obj-y += ldpaa_eth.o >> obj-$(CONFIG_LS2080A) += ls2080a.o >> -obj-$(CONFIG_LS2085A) += ls2080a.o >> diff --git a/include/configs/ls2080a_common.h >> b/include/configs/ls2080a_common.h >> index 13ce349..57e2a29 100644 >> --- a/include/configs/ls2080a_common.h >> +++ b/include/configs/ls2080a_common.h >> @@ -171,10 +171,9 @@ unsigned long long get_qixis_addr(void); >> #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 >> #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 >> #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 >> -#ifdef CONFIG_LS2085A >> +/* For LS2085A */ >> #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 >> #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 >> -#endif > > CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET --> permanent enabled. > > LS2080A (NON-AIOP) personality may execute AIOP code code in driver/net/fsl-mc/mc.c. > Need to put under svr check. Thanks for pointing it out. I overlooked this one. Will update in next version. York
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index cce7405..5f86ef9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif -ifneq ($(CONFIG_LS2085A),) -obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o -endif - ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 4b9e209..d939900 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,12 +538,12 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type, rcw; + u32 type, rcw, svr = gur_in32(&gur->svr); puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); + printf(" %s (0x%x)\n", buf, svr); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); get_sys_info(&sysinfo); puts("Clock Configuration:"); @@ -564,7 +564,10 @@ int print_cpuinfo(void) printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); + if (soc_has_dp_ddr()) { + printf(" DP-DDR: %-4s MT/s", + strmhz(buf, sysinfo.freq_ddrbus2)); + } #endif puts("\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 81cf470..d580a43 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info) FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + if (soc_has_dp_ddr()) { + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; + } else { + sys_info->freq_ddrbus2 = 0; + } #endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 9c69ed1..04831ca 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -20,7 +20,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_FSL_LSCH3 /* Set Wuo bit for RN-I 20 */ -#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) +#ifdef CONFIG_LS2080A ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 213ce3a..d609d81 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -18,7 +18,19 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +bool soc_has_dp_ddr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + /* LS2085A has DP_DDR */ + if (SVR_SOC_VER(svr) == SVR_LS2085) + return true; + + return false; +} + +#ifdef CONFIG_LS2080A /* * This erratum requires setting a value to eddrtqcr1 to * optimal the DDR performance. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index f434c44..c1229c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -54,7 +54,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A env_init(); #endif get_clocks(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index bfaece2..6ca4bc2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -23,16 +23,11 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#endif -#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR -#endif +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 93bbda3..71c428f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -203,7 +203,7 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d1fbde7..f71c2c1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index ea78e15..0916897 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -93,4 +93,6 @@ void cpu_name(char *name); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif + +bool soc_has_dp_ddr(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 56c5d96..1827ddc 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 7bce8b0..e04c02e 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -42,7 +42,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 6f99ad0..3d82482 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -6,5 +6,3 @@ F: board/freescale/ls2080a/ls2080aqds.c F: include/configs/ls2080aqds.h F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig -F: configs/ls2085aqds_defconfig -F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 9fb5e11..fcb0366 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ed9688d 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -227,7 +227,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index c9f3459..aac8110 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -6,5 +6,3 @@ F: board/freescale/ls2080a/ls2080ardb.c F: include/configs/ls2080ardb.h F: configs/ls2080ardb_defconfig F: configs/ls2080ardb_nand_defconfig -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 6c19173..a04d21b 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 12638df..028654c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -197,7 +197,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig deleted file mode 100644 index a5c8388..0000000 --- a/configs/ls2085aqds_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080AQDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_SYS_NS16550=y -CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig deleted file mode 100644 index d355c9a..0000000 --- a/configs/ls2085aqds_nand_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080AQDS=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" -# CONFIG_CMD_SETEXPR is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig deleted file mode 100644 index fe46dbc..0000000 --- a/configs/ls2085ardb_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080ARDB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_SYS_NS16550=y -CONFIG_FSL_DSPI=y diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig deleted file mode 100644 index 5fb0cf6..0000000 --- a/configs/ls2085ardb_nand_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080ARDB=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" -# CONFIG_CMD_SETEXPR is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 74c4916..5587aa6 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -7,4 +7,3 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_LS2080A) += ls2080a.o -obj-$(CONFIG_LS2085A) += ls2080a.o diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 13ce349..57e2a29 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -171,10 +171,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#ifdef CONFIG_LS2085A +/* For LS2085A */ #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 -#endif /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -198,10 +197,6 @@ unsigned long long get_qixis_addr(void); #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" #endif -#ifdef CONFIG_LS2085A -#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" -#endif - #define CONFIG_SYS_PCI_64BIT #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 534ebb6..f4ace85 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -9,15 +9,8 @@ #include "ls2080a_common.h" -#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-EMU" #define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU" -#endif - -#ifdef CONFIG_LS2085A -#define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU" -#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 2c2ce7b..0dbe95f 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -9,15 +9,8 @@ #include "ls2080a_common.h" -#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-SIMU" #define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU" -#endif - -#ifdef CONFIG_LS2085A -#define CONFIG_IDENT_STRING " LS2085A-SIMU" -#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-SIMU" -#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index e922e32..c5e42e6 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -55,7 +55,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#elif defined(CONFIG_LS2080A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++--- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 ++++- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 14 +++++++++- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 +-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++----- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++ board/freescale/ls2080a/ddr.c | 27 +++++++++++--------- board/freescale/ls2080a/ls2080a.c | 2 +- board/freescale/ls2080aqds/MAINTAINERS | 2 -- board/freescale/ls2080aqds/ddr.c | 27 +++++++++++--------- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/ls2080ardb/MAINTAINERS | 2 -- board/freescale/ls2080ardb/ddr.c | 27 +++++++++++--------- board/freescale/ls2080ardb/ls2080ardb.c | 2 +- configs/ls2085aqds_defconfig | 19 -------------- configs/ls2085aqds_nand_defconfig | 14 ---------- configs/ls2085ardb_defconfig | 19 -------------- configs/ls2085ardb_nand_defconfig | 14 ---------- drivers/net/ldpaa_eth/Makefile | 1 - include/configs/ls2080a_common.h | 7 +---- include/configs/ls2080a_emu.h | 7 ----- include/configs/ls2080a_simu.h | 7 ----- include/linux/usb/xhci-fsl.h | 2 +- 27 files changed, 83 insertions(+), 152 deletions(-) delete mode 100644 configs/ls2085aqds_defconfig delete mode 100644 configs/ls2085aqds_nand_defconfig delete mode 100644 configs/ls2085ardb_defconfig delete mode 100644 configs/ls2085ardb_nand_defconfig