[U-Boot,v8,4/9] drivers: pinctrl: Add simple pinctrl driver for QCA/Athores ar933x.

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2a69bab..854d5a5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -105,6 +105,15 @@  config SPL_PINCONF
 
 if PINCTRL || SPL_PINCTRL
 
+config AR933X_PINCTRL
+	bool "QCA/Athores ar933x pin control driver"
+	depends on DM && SOC_AR933X
+	help
+	  Support pin multiplexing control on QCA/Athores ar933x SoCs.
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
 config ROCKCHIP_PINCTRL
 	bool "Rockchip pin control driver"
 	depends on DM
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 37dc904..b99ed2f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -6,6 +6,7 @@  obj-y					+= pinctrl-uclass.o
 obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC)	+= pinctrl-generic.o
 
 obj-y					+= nxp/
+obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
diff --git a/drivers/pinctrl/ath79/Makefile b/drivers/pinctrl/ath79/Makefile
new file mode 100644
index 0000000..3fdcf6c
--- /dev/null
+++ b/drivers/pinctrl/ath79/Makefile
@@ -0,0 +1,5 @@ 
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
diff --git a/drivers/pinctrl/ath79/pinctrl_ar933x.c b/drivers/pinctrl/ath79/pinctrl_ar933x.c
new file mode 100644
index 0000000..e3f64b6
--- /dev/null
+++ b/drivers/pinctrl/ath79/pinctrl_ar933x.c
@@ -0,0 +1,136 @@ 
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+	PERIPH_ID_UART0,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_NONE = -1,
+};
+
+struct ar933x_pinctrl_priv {
+	void __iomem *regs;
+};
+
+static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
+{
+	switch (cs) {
+	case 0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(4), AR933X_GPIO(3) |
+				AR933X_GPIO(5) | AR933X_GPIO(2));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_SPI_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(9), AR933X_GPIO(10));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_UART_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_SPI0:
+		pinctrl_ar933x_spi_config(priv, flags);
+		break;
+	case PERIPH_ID_UART0:
+		pinctrl_ar933x_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[2];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[0]) {
+	case 128:
+		return PERIPH_ID_UART0;
+	case 129:
+		return PERIPH_ID_SPI0;
+	}
+	return -ENOENT;
+}
+
+static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = ar933x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return ar933x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops ar933x_pinctrl_ops = {
+	.set_state_simple	= ar933x_pinctrl_set_state_simple,
+	.request	= ar933x_pinctrl_request,
+	.get_periph_id	= ar933x_pinctrl_get_periph_id,
+};
+
+static int ar933x_pinctrl_probe(struct udevice *dev)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_GPIO_SIZE,
+				 MAP_NOCACHE);
+	return 0;
+}
+
+static const struct udevice_id ar933x_pinctrl_ids[] = {
+	{ .compatible = "qca,ar933x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_ar933x) = {
+	.name		= "pinctrl_ar933x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= ar933x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
+	.ops		= &ar933x_pinctrl_ops,
+	.probe		= ar933x_pinctrl_probe,
+};