From patchwork Thu Jul 22 07:11:01 2010
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Subject: [PATCH:, PR, target/44999] Replace "and r0, r0,
 #255" with uxtb in thumb2
Date: Wed, 21 Jul 2010 21:11:01 -0000
From: Carrot Wei <carrot@google.com>
X-Patchwork-Id: 59544
Message-Id: <AANLkTinA9B9PuMdEvoNG4h7wnRd9egzqBNuUChFMJ+S1@mail.gmail.com>
To: gcc-patches@gcc.gnu.org

In thumb2 "and r0, r0, #255" is 32 bit, uxtb is 16 bit and does the same
operation. This patch simply detect the situation in pattern "andsi3" and call
gen_thumb2_zero_extendqisi2_v6.

Tested on arm qemu.

ChangeLog:
2010-07-22  Wei Guozhi  <carrot@google.com>

        PR target/44999
        * config/arm/arm.md (andsi3): Change to zero extension if possible.
        * config/arm/thumb2.md (thumb2_zero_extendqisi2_v6): Change the name.

ChangeLog:
2010-07-22  Wei Guozhi  <carrot@google.com>

        PR target/44999
        * gcc.target/arm/pr44999.c: New testcase.


Index: thumb2.md
===================================================================
--- thumb2.md   (revision 162396)
+++ thumb2.md   (working copy)
@@ -970,7 +970,7 @@
    (set_attr "neg_pool_range" "*,250")]
 )

-(define_insn "*thumb2_zero_extendqisi2_v6"
+(define_insn "thumb2_zero_extendqisi2_v6"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
   "TARGET_THUMB2 && arm_arch6"


Index: arm.md
===================================================================
--- arm.md      (revision 162396)
+++ arm.md      (working copy)
@@ -1933,9 +1933,16 @@
     {
       if (GET_CODE (operands[2]) == CONST_INT)
         {
-          arm_split_constant (AND, SImode, NULL_RTX,
-                             INTVAL (operands[2]), operands[0],
-                             operands[1], optimize && can_create_pseudo_p ());
+         if (INTVAL (operands[2]) == 255 && arm_arch6)
+           {
+             operands[1] = gen_rtx_SUBREG (QImode, operands[1], 0);
+             gen_thumb2_zero_extendqisi2_v6 (operands[0], operands[1]);
+           }
+         else
+           arm_split_constant (AND, SImode, NULL_RTX,
+                               INTVAL (operands[2]), operands[0],
+                               operands[1],
+                               optimize && can_create_pseudo_p ());

           DONE;
         }

		
Index: pr44999.c
===================================================================
--- pr44999.c   (revision 0)
+++ pr44999.c   (revision 0)
@@ -0,0 +1,7 @@
+/* { dg-options "-march=armv7-a -mthumb -Os" }  */
+/* { dg-final { scan-assembler "uxtb" } } */
+
+int tp(int x, int y)
+{
+  return (x & 0xff) - (y & 0xffff);
+}