From patchwork Tue Jul 20 20:45:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [rs6000] disable mfcr pattern for TARGET_ISEL Date: Tue, 20 Jul 2010 10:45:06 -0000 From: Nathan Froyd X-Patchwork-Id: 59371 Message-Id: <20100720204506.GN26037@codesourcery.com> To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com mfcr can be a slow instruction, particular for multiple-issue processors, where it requires serializing the instruction stream to ensure that CR has been properly updated. The primary pattern where mfcr occurs deals with moving an individual bit from CR to a GPR. This pattern not only uses mfcr, but also binds the mfcr and accompanying rlwinm together instead of permitting them to be scheduled separately. On TARGET_ISEL processors, however, we can improve the matter somewhat by using isel instead of mfcr. With isel, there's no need to synchronize on CR as a whole, just an individual field. The instructions that load zero and one can also be scheduled separately from the isel itself. The patch below enables this improvement by turning off the aforementioned mfcr/rlwinm pattern for TARGET_ISEL processors. The patch could be improved; there's a TARGET_POWERPC64 pattern that's identical save for the modes of registers slightly further on in the file. I don't have a power7 system to test the equivalent 64-bit path on, but if somebody was willing to test on such a system for me, I could tweak the patch accordingly. (Such a tweaked patch could also use mode iterators, which would be an improvement.) Tested with cross to powerpc-eabispe. OK to commit? -Nathan * config/rs6000/rs6000.md (define_insn ""): Enable only for !TARGET_ISEL targets. Index: config/rs6000/rs6000.md =================================================================== --- config/rs6000/rs6000.md (revision 162348) +++ config/rs6000/rs6000.md (working copy) @@ -13052,7 +13052,7 @@ (define_insn "" (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]))] - "" + "!TARGET_ISEL" "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" [(set (attr "type") (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))