Patchwork [v2,1/2] seabios: shadow: make device finding more generic.

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Submitter Isaku Yamahata
Date July 20, 2010, 7:50 a.m.
Message ID <1f291e25a69f673c7ee618c9838b99b95e9c5cc2.1279612021.git.yamahata@valinux.co.jp>
Download mbox | patch
Permalink /patch/59288/
State New
Headers show

Comments

Isaku Yamahata - July 20, 2010, 7:50 a.m.
pam register offset is north bridge specific.
So determine the offset based on found north bridge.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
changes v2 -> v3.
- abstract at device level, not at register offset level.
- factor out intel chipset operation.
---
 src/dev-i440fx.c |   12 ++++++
 src/dev-i440fx.h |    2 +
 src/shadow.c     |  106 +++++++++++++++++++++++++++++++++---------------------
 src/util.h       |    2 +
 4 files changed, 81 insertions(+), 41 deletions(-)

Patch

diff --git a/src/dev-i440fx.c b/src/dev-i440fx.c
index 15c6cac..366a2db 100644
--- a/src/dev-i440fx.c
+++ b/src/dev-i440fx.c
@@ -17,6 +17,18 @@ 
 #include "acpi.h"
 #include "dev-i440fx.h"
 
+#define I440FX_PAM0     0x59
+
+void i440fx_bios_make_writable(u16 bdf, void *arg)
+{
+    make_bios_writable_intel(bdf, I440FX_PAM0);
+}
+
+void i440fx_bios_make_readonly(u16 bdf, void *arg)
+{
+    make_bios_readonly_intel(bdf, I440FX_PAM0);
+}
+
 /* PIIX3/PIIX4 PCI to ISA bridge */
 void piix_isa_bridge_init(u16 bdf, void *arg)
 {
diff --git a/src/dev-i440fx.h b/src/dev-i440fx.h
index 661860a..6d1b687 100644
--- a/src/dev-i440fx.h
+++ b/src/dev-i440fx.h
@@ -3,6 +3,8 @@ 
 
 #include "types.h" // u16
 
+void i440fx_bios_make_writable(u16 bdf, void *arg);
+void i440fx_bios_make_readonly(u16 bdf, void *arg);
 void piix_isa_bridge_init(u16 bdf, void *arg);
 void piix_ide_init(u16 bdf, void *arg);
 void piix4_pm_init(u16 bdf, void *arg);
diff --git a/src/shadow.c b/src/shadow.c
index 978424e..e91e54e 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -9,6 +9,7 @@ 
 #include "pci.h" // pci_config_writeb
 #include "config.h" // CONFIG_*
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "dev-i440fx.h"
 
 // Test if 'addr' is in the range from 'start'..'start+size'
 #define IN_RANGE(addr, start, size) ({   \
@@ -23,30 +24,31 @@ 
 
 // Enable shadowing and copy bios.
 static void
-__make_bios_writable(u16 bdf)
+__make_bios_writable_intel(u16 bdf, u32 pam0)
 {
     // Make ram from 0xc0000-0xf0000 writable
     int clear = 0;
     int i;
     for (i=0; i<6; i++) {
-        int reg = pci_config_readb(bdf, 0x5a + i);
+      u32 pam = pam0 + 1 + i;
+      int reg = pci_config_readb(bdf, pam);
         if ((reg & 0x11) != 0x11) {
             // Need to copy optionroms to work around qemu implementation
             void *mem = (void*)(BUILD_ROM_START + i * 32*1024);
             memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024);
-            pci_config_writeb(bdf, 0x5a + i, 0x33);
+            pci_config_writeb(bdf, pam, 0x33);
             memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024);
             clear = 1;
         } else {
-            pci_config_writeb(bdf, 0x5a + i, 0x33);
+            pci_config_writeb(bdf, pam, 0x33);
         }
     }
     if (clear)
         memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
 
     // Make ram from 0xf0000-0x100000 writable
-    int reg = pci_config_readb(bdf, 0x59);
-    pci_config_writeb(bdf, 0x59, 0x30);
+    int reg = pci_config_readb(bdf, pam0);
+    pci_config_writeb(bdf, pam0, 0x30);
     if (reg & 0x10)
         // Ram already present.
         return;
@@ -55,52 +57,28 @@  __make_bios_writable(u16 bdf)
     memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
 }
 
-// Make the 0xc0000-0x100000 area read/writable.
 void
-make_bios_writable(void)
+make_bios_writable_intel(u16 bdf, u32 pam0)
 {
-    if (CONFIG_COREBOOT)
-        return;
-
-    dprintf(3, "enabling shadow ram\n");
-
-    // Locate chip controlling ram shadowing.
-    int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
-    if (bdf < 0) {
-        dprintf(1, "Unable to unlock ram - bridge not found\n");
-        return;
-    }
-
-    int reg = pci_config_readb(bdf, 0x59);
+    int reg = pci_config_readb(bdf, pam0);
     if (!(reg & 0x10)) {
         // QEMU doesn't fully implement the piix shadow capabilities -
         // if ram isn't backing the bios segment when shadowing is
         // disabled, the code itself wont be in memory.  So, run the
         // code from the high-memory flash location.
-        u32 pos = (u32)__make_bios_writable - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
-        void (*func)(u16 bdf) = (void*)pos;
-        func(bdf);
+        u32 pos = (u32)__make_bios_writable_intel - BUILD_BIOS_ADDR +
+            BIOS_SRC_ADDR;
+        void (*func)(u16 bdf, u32 pam0) = (void*)pos;
+        func(bdf, pam0);
         return;
     }
     // Ram already present - just enable writes
-    __make_bios_writable(bdf);
+    __make_bios_writable_intel(bdf, pam0);
 }
 
-// Make the BIOS code segment area (0xf0000) read-only.
 void
-make_bios_readonly(void)
+make_bios_readonly_intel(u16 bdf, u32 pam0)
 {
-    if (CONFIG_COREBOOT)
-        return;
-
-    dprintf(3, "locking shadow ram\n");
-
-    int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
-    if (bdf < 0) {
-        dprintf(1, "Unable to lock ram - bridge not found\n");
-        return;
-    }
-
     // Flush any pending writes before locking memory.
     wbinvd();
 
@@ -108,14 +86,60 @@  make_bios_readonly(void)
     int i;
     for (i=0; i<6; i++) {
         u32 mem = BUILD_ROM_START + i * 32*1024;
+        u32 pam = pam0 + 1 + i;
         if (RomEnd <= mem + 16*1024) {
             if (RomEnd > mem)
-                pci_config_writeb(bdf, 0x5a + i, 0x31);
+                pci_config_writeb(bdf, pam, 0x31);
             break;
         }
-        pci_config_writeb(bdf, 0x5a + i, 0x11);
+        pci_config_writeb(bdf, pam, 0x11);
     }
 
     // Write protect 0xf0000-0x100000
-    pci_config_writeb(bdf, 0x59, 0x10);
+    pci_config_writeb(bdf, pam0, 0x10);
+}
+
+static const struct pci_device_id dram_controller_make_writable_tbl[] = {
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
+               i440fx_bios_make_writable),
+    PCI_DEVICE_END
+};
+
+// Make the 0xc0000-0x100000 area read/writable.
+void
+make_bios_writable(void)
+{
+    if (CONFIG_COREBOOT)
+        return;
+
+    dprintf(3, "enabling shadow ram\n");
+
+    // at this point, staticlly alloacted variable can't written.
+    // so stack should be used.
+
+    // Locate chip controlling ram shadowing.
+    int bdf = pci_find_init_device(dram_controller_make_writable_tbl, NULL);
+    if (bdf < 0) {
+        dprintf(1, "Unable to unlock ram - bridge not found\n");
+    }
+}
+
+static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
+               i440fx_bios_make_readonly),
+    PCI_DEVICE_END
+};
+
+// Make the BIOS code segment area (0xf0000) read-only.
+void
+make_bios_readonly(void)
+{
+    if (CONFIG_COREBOOT)
+        return;
+
+    dprintf(3, "locking shadow ram\n");
+    int bdf = pci_find_init_device(dram_controller_make_readonly_tbl, NULL);
+    if (bdf < 0) {
+        dprintf(1, "Unable to lock ram - bridge not found\n");
+    }
 }
diff --git a/src/util.h b/src/util.h
index 6c08a3c..96f4ff7 100644
--- a/src/util.h
+++ b/src/util.h
@@ -332,6 +332,8 @@  void bios32_setup(void);
 // shadow.c
 void make_bios_writable(void);
 void make_bios_readonly(void);
+void make_bios_writable_intel(u16 bdf, u32 pam0);
+void make_bios_readonly_intel(u16 bdf, u32 pam0);
 
 // pciinit.c
 extern const u8 pci_irqs[4];