| Message ID | 1457317732-18406-30-git-send-email-sjg@chromium.org |
|---|---|
| State | Accepted |
| Commit | 963a811ab42aac2fac6fc063dc7cc689a3336d28 |
| Delegated to: | Bin Meng |
| Headers | show |
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <sjg@chromium.org> wrote: > At present the board ID GPIOs are hard-coded. Move them to the device tree > so that we can use general SDRAM init code. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/dts/chromebook_link.dts | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Fri, Mar 11, 2016 at 1:52 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <sjg@chromium.org> wrote: >> At present the board ID GPIOs are hard-coded. Move them to the device tree >> so that we can use general SDRAM init code. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> arch/x86/dts/chromebook_link.dts | 2 ++ >> 1 file changed, 2 insertions(+) >> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> applied to u-boot-x86/next, thanks!
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 12f315e..a702ea9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -74,6 +74,8 @@ northbridge@0,0 { reg = <0x00000000 0 0 0 0>; compatible = "intel,bd82x6x-northbridge"; + board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>, + <&gpio_b 11 0>, <&gpio_a 10 0>; u-boot,dm-pre-reloc; spd { compatible = "memory-spd";
At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/dts/chromebook_link.dts | 2 ++ 1 file changed, 2 insertions(+)