From patchwork Sat Mar 5 15:42:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vishnupatekar X-Patchwork-Id: 592391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 526D51402C4 for ; Sun, 6 Mar 2016 02:46:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=zliNAGIE; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755064AbcCEPoE (ORCPT ); Sat, 5 Mar 2016 10:44:04 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:32848 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754712AbcCEPnr (ORCPT ); Sat, 5 Mar 2016 10:43:47 -0500 Received: by mail-pf0-f193.google.com with SMTP id 63so5040855pfe.0; Sat, 05 Mar 2016 07:43:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/m8idAr1kU+KhUYmdivniGsGM+g1dwsZ4y73X0UE6jo=; b=zliNAGIEkIBwn+nmv13JbvDyLbU3uX1n7j8hKOv/udHdSgzA+0ZHg2KXMRGz4wWEjc dmgQkQhq2wKA0PuBOcqVAAOH6CUN9ik2VBbE6beeeJB6+HxyNCQ6sO9Y/iOuMmc30ioI smaxhOxaKHA7+t9zJN6RnfeHT9K3ePY2x5FE9hDhV+dnCODcHnSxZONPYBh8RgqMUU1+ bndEpDdIT9uqzl0SGGtdKWeclVbICUN0oHNr4VGKS3nUSMg3LtgoceP1JpSk1CStjwD1 9e2VUFTF1D/J9OrMZqHT3x/wlTRDB7GijyiyPPwONpAGW6rsbNPiKyrvQpqELsPgb50L raEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/m8idAr1kU+KhUYmdivniGsGM+g1dwsZ4y73X0UE6jo=; b=Ynw4hfCtEulxQHNLSJiG5i7U1IqmAJ/zsKdcQapdqDctNcyV3kwG1uxmHhrvvrnFFz qr4/2oDNpJrhzlhwSZC9LqWBJbehn2TMuMKSFgI3y7pCOh72T934zBkFSpu/S9Wx/6TH 52+RVGiMAY2LhGfOFEBZoC2KvDApWyZuw7eg7GW2OBQl8066JzII001rBUSQx1IeRJJ1 RsdObWdtK1RpzIozua98qPhJPOQwnEy1A+AdrW4OcqMCGhoa+69m9Mf5w+sx1cy1388w GctvK4NcNuAUaejrlSWPAGcJeISe1Po7W1UJNVeo9AXDA5nZIc2FQsTHAUHA4AIxjfkL eTDw== X-Gm-Message-State: AD7BkJIiHmzBWbKlrGp+jV1fSwpEPkHi0YZyrBYTwd5g9OO/GWVd/bCp1w6fFmrPVle2qA== X-Received: by 10.98.64.82 with SMTP id n79mr20694668pfa.149.1457192625861; Sat, 05 Mar 2016 07:43:45 -0800 (PST) Received: from localhost.localdomain ([101.127.161.160]) by smtp.gmail.com with ESMTPSA id ah10sm13230527pad.23.2016.03.05.07.43.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Mar 2016 07:43:45 -0800 (PST) From: Vishnu Patekar To: robh+dt@kernel.org, corbet@lwn.net, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, maxime.ripard@free-electrons.com, linux@arm.linux.org.uk, emilio@elopez.com.ar Cc: jenskuske@gmail.com, hdegoede@redhat.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, mturquette@baylibre.com, sboyd@codeaurora.org, patchesrdh@mveas.com, linux-clk@vger.kernel.org Subject: [PATCH v3 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets Date: Sat, 5 Mar 2016 23:42:57 +0800 Message-Id: <1457192586-25596-5-git-send-email-vishnupatekar0510@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457192586-25596-1-git-send-email-vishnupatekar0510@gmail.com> References: <1457192586-25596-1-git-send-email-vishnupatekar0510@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds A83T system bus clocks, bus gates, and clock resets. Three ahb reset registers are combined into one node. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +++++++++++++++++++++++++++++++++++++- 1 file changed, 112 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index d3473f8..2689af4 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -146,6 +146,97 @@ clocks = <&osc16M>; clock-output-names = "osc16M-d512"; }; + + pll6: clk@01c20028 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6"; + }; + + pll6d2: pll6d2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll6>; + clock-output-names = "pll6d2"; + }; + + ahb1: clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a83t-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "ahb1"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a83t-apb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "apb2"; + }; + + ahb2: clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a83t-bus-gates-clk"; + reg = <0x01c20060 0x10>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <1>, <5>, <6>, + <8>, <9>, <10>, + <13>, <14>, <17>, + <19>, <20>, + <21>, <24>, + <26>, <27>, + <29>, <32>, + <36>, <37>, + <40>, <43>, + <44>, <52>, <53>, + <54>, <65>, + <69>, <76>, <77>, + <78>, <79>, <96>, + <97>, <98>, + <112>, <113>, + <114>, <115>, + <116>; + clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma", + "bus_mmc0", "bus_mmc1", "bus_mmc2", + "bus_nand", "bus_sdram", "bus_emac", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_usb_otg", + "bus_ehci0", "bus_ehci1", + "bus_ohci0", "bus_ve", + "bus_lcd0", "bus_lcd1", + "bus_csi", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_spdif", + "bus_pio", "bus_i2s0", "bus_i2s1", + "bus_i2s2", "bus_tdm", "bus_i2c0", + "bus_i2c1", "bus_i2c2", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_uart4"; + }; }; soc { @@ -160,7 +251,7 @@ , ; reg = <0x01c20800 0x400>; - clocks = <&osc24M>; + clocks = <&bus_gates 69>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -189,6 +280,24 @@ }; }; + ahb_reset: reset@01c202c0 { + reg = <0x01c202c0 0xc>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + + apb1_reset: reset@01c202d0 { + reg = <0x01c202d0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + + apb2_reset: reset@01c202d8 { + reg = <0x01c202d8 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; @@ -210,7 +319,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&bus_gates 112>; + resets = <&apb2_reset 16>; status = "disabled"; };