Patchwork [net-next-2.6] e1000: allow option to limit number of descriptors down to 48 per ring

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Submitter Jeff Kirsher
Date July 19, 2010, 11:43 p.m.
Message ID <20100719234219.13875.90302.stgit@localhost.localdomain>
Download mbox | patch
Permalink /patch/59233/
State Accepted
Delegated to: David Miller
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Comments

Jeff Kirsher - July 19, 2010, 11:43 p.m.
From: Alexander Duyck <alexander.h.duyck@intel.com>

This change makes it possible to limit the number of descriptors down to 48
per ring.  The reason for this change is to address a variation on hardware
errata 10 for 82546GB in which descriptors will be lost if more than 32
descriptors are fetched and the PCI-X MRBC is 512.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Emil Tantilov <emil.s.tantilov@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---

 drivers/net/e1000/e1000.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


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David Miller - July 20, 2010, 3:24 a.m.
From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Date: Mon, 19 Jul 2010 16:43:47 -0700

> From: Alexander Duyck <alexander.h.duyck@intel.com>
> 
> This change makes it possible to limit the number of descriptors down to 48
> per ring.  The reason for this change is to address a variation on hardware
> errata 10 for 82546GB in which descriptors will be lost if more than 32
> descriptors are fetched and the PCI-X MRBC is 512.
> 
> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
> Tested-by: Emil Tantilov <emil.s.tantilov@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

Applied.
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Eric Dumazet - July 20, 2010, 4:40 a.m.
Le lundi 19 juillet 2010 à 16:43 -0700, Jeff Kirsher a écrit :
> From: Alexander Duyck <alexander.h.duyck@intel.com>
> 
> This change makes it possible to limit the number of descriptors down to 48
> per ring.  The reason for this change is to address a variation on hardware
> errata 10 for 82546GB in which descriptors will be lost if more than 32
> descriptors are fetched and the PCI-X MRBC is 512.
> 
> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
> Tested-by: Emil Tantilov <emil.s.tantilov@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
> ---
> 
>  drivers/net/e1000/e1000.h |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
> index 40b62b4..65298a6 100644
> --- a/drivers/net/e1000/e1000.h
> +++ b/drivers/net/e1000/e1000.h
> @@ -86,12 +86,12 @@ struct e1000_adapter;
>  /* TX/RX descriptor defines */
>  #define E1000_DEFAULT_TXD                  256
>  #define E1000_MAX_TXD                      256
> -#define E1000_MIN_TXD                       80
> +#define E1000_MIN_TXD                       48
>  #define E1000_MAX_82544_TXD               4096
>  
>  #define E1000_DEFAULT_RXD                  256
>  #define E1000_MAX_RXD                      256
> -#define E1000_MIN_RXD                       80
> +#define E1000_MIN_RXD                       48
>  #define E1000_MAX_82544_RXD               4096
>  
>  #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
> 

So this limit is a pure software one ?

Why not let an admin chose a lower limit if he wants to ?

I am asking because big ring sizes can be a latency source in some
workloads.

Thanks


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Jesse Brandeburg - July 20, 2010, 5:12 p.m.
On Mon, 19 Jul 2010, Eric Dumazet wrote:

> Le lundi 19 juillet 2010 à 16:43 -0700, Jeff Kirsher a écrit :
> > From: Alexander Duyck <alexander.h.duyck@intel.com>
> > 
> > This change makes it possible to limit the number of descriptors down to 48
> > per ring.  The reason for this change is to address a variation on hardware
> > errata 10 for 82546GB in which descriptors will be lost if more than 32
> > descriptors are fetched and the PCI-X MRBC is 512.
> > -#define E1000_MIN_TXD                       80
> > +#define E1000_MIN_TXD                       48
> >  #define E1000_MAX_82544_TXD               4096
> >  
> >  #define E1000_DEFAULT_RXD                  256
> >  #define E1000_MAX_RXD                      256
> > -#define E1000_MIN_RXD                       80
> > +#define E1000_MIN_RXD                       48
> >  #define E1000_MAX_82544_RXD               4096

> So this limit is a pure software one ?

Yes, the hardware will work fine (with the exception of some limits when 
certain performance registers are configured like [TR]XDCTL) all the way 
down to 1 descriptor, that said, the practical limit is probably more like 
8 for RX descriptors, and is 2 * (MAX_SKB_FRAGS + 1) for transmit if TSO 
is enabled.

if all offloads are disabled you could run with only 8 tx descriptors, and 
I believe it would work fine.

> Why not let an admin chose a lower limit if he wants to ?

I think in this case just to prevent odd interaction bugs with low values 
(there would have to be several driver changes and the testing work would 
increase to support very low values)

> I am asking because big ring sizes can be a latency source in some
> workloads.

yes, if you are trying to pace traffic in software.  That said, at least 
on transmit, most frames exit immediately from the hardware unless some 
external event like flow control is slowing down transmit.

Jesse
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Patch

diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 40b62b4..65298a6 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -86,12 +86,12 @@  struct e1000_adapter;
 /* TX/RX descriptor defines */
 #define E1000_DEFAULT_TXD                  256
 #define E1000_MAX_TXD                      256
-#define E1000_MIN_TXD                       80
+#define E1000_MIN_TXD                       48
 #define E1000_MAX_82544_TXD               4096
 
 #define E1000_DEFAULT_RXD                  256
 #define E1000_MAX_RXD                      256
-#define E1000_MIN_RXD                       80
+#define E1000_MIN_RXD                       48
 #define E1000_MAX_82544_RXD               4096
 
 #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */