| Message ID | 1456778767-18413-2-git-send-email-dev@lynxeye.de |
|---|---|
| State | Accepted |
| Headers | show |
On Mon, Feb 29, 2016 at 09:46:07PM +0100, Lucas Stach wrote: > The post divider value in the frequency table is wrong as it > would lead to the PLL producing a output rate of 960MHz instead > of the desired 480MHz. This wasn't a problem as nothing used the > table to actually init the PLL rate, but the bootloader > configuration was used unaltered. > > If the bootloader does not set up the PLL it will fail to come > when used under Linux. To fix this don't rely on the bootloader, > but set the correct rate in the clock driver. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > drivers/clk/tegra/clk-tegra30.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) Applied, thanks. Thierry
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 236e2db..9396f49 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -339,11 +339,11 @@ static const struct pdiv_map pllu_p[] = { }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 1, 12 }, - { 13000000, 480000000, 960, 13, 1, 12 }, - { 16800000, 480000000, 400, 7, 1, 5 }, - { 19200000, 480000000, 200, 4, 1, 3 }, - { 26000000, 480000000, 960, 26, 1, 12 }, + { 12000000, 480000000, 960, 12, 2, 12 }, + { 13000000, 480000000, 960, 13, 2, 12 }, + { 16800000, 480000000, 400, 7, 2, 5 }, + { 19200000, 480000000, 200, 4, 2, 3 }, + { 26000000, 480000000, 960, 26, 2, 12 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -1380,6 +1380,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, + { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, };
The post divider value in the frequency table is wrong as it would lead to the PLL producing a output rate of 960MHz instead of the desired 480MHz. This wasn't a problem as nothing used the table to actually init the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by: Lucas Stach <dev@lynxeye.de> --- drivers/clk/tegra/clk-tegra30.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)