diff mbox

thermal: tegra_soctherm: fix sign bit of temperature

Message ID 1456739480-3304-1-git-send-email-wni@nvidia.com
State Accepted, archived
Headers show

Commit Message

Wei Ni Feb. 29, 2016, 9:51 a.m. UTC
The sign bit of temperature readback is bit 0, not bit 1.
Change to BIT(0) to fix it.

Signed-off-by: Wei Ni <wni@nvidia.com>
---
 drivers/thermal/tegra_soctherm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Wei Ni March 2, 2016, 7:40 a.m. UTC | #1
Hi, Rui & Thierry & Matt
Could you please take a look on this patch.
It's a bug on the temperature's sign bit, it can't show the negative
temperature, although it will not cause problems for now.

Thanks.
Wei.

On 2016年02月29日 17:51, Wei Ni wrote:
> The sign bit of temperature readback is bit 0, not bit 1.
> Change to BIT(0) to fix it.
> 
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
>  drivers/thermal/tegra_soctherm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> index 74ea5765938b..136975220c92 100644
> --- a/drivers/thermal/tegra_soctherm.c
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -57,7 +57,7 @@
>  #define READBACK_VALUE_MASK			0xff00
>  #define READBACK_VALUE_SHIFT			8
>  #define READBACK_ADD_HALF			BIT(7)
> -#define READBACK_NEGATE				BIT(1)
> +#define READBACK_NEGATE				BIT(0)
>  
>  #define FUSE_TSENSOR8_CALIB			0x180
>  #define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc
> 
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Matthew Longnecker March 3, 2016, 12:08 a.m. UTC | #2
On 03/01/2016 11:40 PM, Wei Ni wrote:
> >diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> >index 74ea5765938b..136975220c92 100644
> >--- a/drivers/thermal/tegra_soctherm.c
> >+++ b/drivers/thermal/tegra_soctherm.c
> >@@ -57,7 +57,7 @@
> >  #define READBACK_VALUE_MASK			0xff00
> >  #define READBACK_VALUE_SHIFT			8
> >  #define READBACK_ADD_HALF			BIT(7)
> >-#define READBACK_NEGATE				BIT(1)
> >+#define READBACK_NEGATE				BIT(0)
I confirm that this change is technically correct. It fixes a bug.
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Wei Ni March 7, 2016, 8:26 a.m. UTC | #3
Hi, Rui and Thierry
Could you please take a look at this patch?

Thanks.
Wei.

On 2016年03月03日 08:08, Matt Longnecker wrote:
> 
> 
> On 03/01/2016 11:40 PM, Wei Ni wrote:
>> >diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
>> >index 74ea5765938b..136975220c92 100644
>> >--- a/drivers/thermal/tegra_soctherm.c
>> >+++ b/drivers/thermal/tegra_soctherm.c
>> >@@ -57,7 +57,7 @@
>> >  #define READBACK_VALUE_MASK            0xff00
>> >  #define READBACK_VALUE_SHIFT            8
>> >  #define READBACK_ADD_HALF            BIT(7)
>> >-#define READBACK_NEGATE                BIT(1)
>> >+#define READBACK_NEGATE                BIT(0)
> I confirm that this change is technically correct. It fixes a bug.
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Thierry Reding March 7, 2016, 8:32 a.m. UTC | #4
On Wed, Mar 02, 2016 at 04:08:33PM -0800, Matt Longnecker wrote:
> 
> 
> On 03/01/2016 11:40 PM, Wei Ni wrote:
> >>diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> >>index 74ea5765938b..136975220c92 100644
> >>--- a/drivers/thermal/tegra_soctherm.c
> >>+++ b/drivers/thermal/tegra_soctherm.c
> >>@@ -57,7 +57,7 @@
> >>  #define READBACK_VALUE_MASK			0xff00
> >>  #define READBACK_VALUE_SHIFT			8
> >>  #define READBACK_ADD_HALF			BIT(7)
> >>-#define READBACK_NEGATE				BIT(1)
> >>+#define READBACK_NEGATE				BIT(0)
> I confirm that this change is technically correct. It fixes a bug.

That usually translates to a Reviewed-by: tag. =)

Thierry
Thierry Reding March 7, 2016, 8:38 a.m. UTC | #5
On Mon, Feb 29, 2016 at 05:51:20PM +0800, Wei Ni wrote:
> The sign bit of temperature readback is bit 0, not bit 1.
> Change to BIT(0) to fix it.
> 
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
>  drivers/thermal/tegra_soctherm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
> index 74ea5765938b..136975220c92 100644
> --- a/drivers/thermal/tegra_soctherm.c
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -57,7 +57,7 @@
>  #define READBACK_VALUE_MASK			0xff00
>  #define READBACK_VALUE_SHIFT			8
>  #define READBACK_ADD_HALF			BIT(7)
> -#define READBACK_NEGATE				BIT(1)
> +#define READBACK_NEGATE				BIT(0)

I haven't found this documented anywhere. The register documentation
indicates that the SOC_THERM_TSENSOR_TEMP1 and SOC_THERM_TSENSOR_TEMP2
registers are in some kind of "temp readback format", but I can't find
any specification of that format. Can you point me at the source for
this information and file an internal bug report so that we can get
the documentation updated?

Thierry
Wei Ni March 7, 2016, 8:45 a.m. UTC | #6
On 2016年03月07日 16:38, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Feb 29, 2016 at 05:51:20PM +0800, Wei Ni wrote:
>> The sign bit of temperature readback is bit 0, not bit 1.
>> Change to BIT(0) to fix it.
>>
>> Signed-off-by: Wei Ni <wni@nvidia.com>
>> ---
>>  drivers/thermal/tegra_soctherm.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
>> index 74ea5765938b..136975220c92 100644
>> --- a/drivers/thermal/tegra_soctherm.c
>> +++ b/drivers/thermal/tegra_soctherm.c
>> @@ -57,7 +57,7 @@
>>  #define READBACK_VALUE_MASK			0xff00
>>  #define READBACK_VALUE_SHIFT			8
>>  #define READBACK_ADD_HALF			BIT(7)
>> -#define READBACK_NEGATE				BIT(1)
>> +#define READBACK_NEGATE				BIT(0)
> 
> I haven't found this documented anywhere. The register documentation
> indicates that the SOC_THERM_TSENSOR_TEMP1 and SOC_THERM_TSENSOR_TEMP2
> registers are in some kind of "temp readback format", but I can't find
> any specification of that format. Can you point me at the source for
> this information and file an internal bug report so that we can get
> the documentation updated?

Sure, I will do it.
Thanks for your comment.

> 
> Thierry
> 
> * Unknown Key
> * 0x7F3EB3A1
> 
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Wei Ni March 7, 2016, 9:16 a.m. UTC | #7
On 2016年03月07日 16:55, Zhang, Rui wrote:
> For the soc thermal driver changes, you'd better cc Eduardo at the same time so that he can include this in his soc-thermal pull request.
> Surely I can queue this for 4.6 if Eduardo miss this.

Thanks for your help.

BTW, please add:
Reviewed-by: Matt Longnecker <mlongnecker@nvidia.com>

Or I need to send v2 patch to add it?

Thanks.
Wei.

> 
> Thanks,
> rui
> 
>> -----Original Message-----
>> From: Wei Ni [mailto:wni@nvidia.com]
>> Sent: Monday, March 07, 2016 4:26 PM
>> To: thierry.reding@gmail.com; Zhang, Rui <rui.zhang@intel.com>;
>> mikko.perttunen@kapsi.fi
>> Cc: Matt Longnecker <mlongnecker@nvidia.com>; swarren@wwwdotorg.org;
>> linux-tegra@vger.kernel.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH] thermal: tegra_soctherm: fix sign bit of temperature
>> Importance: High
>>
>> Hi, Rui and Thierry
>> Could you please take a look at this patch?
>>
>> Thanks.
>> Wei.
>>
>> On 2016年03月03日 08:08, Matt Longnecker wrote:
>>>
>>>
>>> On 03/01/2016 11:40 PM, Wei Ni wrote:
>>>>> diff --git a/drivers/thermal/tegra_soctherm.c
>> b/drivers/thermal/tegra_soctherm.c
>>>>> index 74ea5765938b..136975220c92 100644
>>>>> --- a/drivers/thermal/tegra_soctherm.c
>>>>> +++ b/drivers/thermal/tegra_soctherm.c
>>>>> @@ -57,7 +57,7 @@
>>>>>  #define READBACK_VALUE_MASK            0xff00
>>>>>  #define READBACK_VALUE_SHIFT            8
>>>>>  #define READBACK_ADD_HALF            BIT(7)
>>>>> -#define READBACK_NEGATE                BIT(1)
>>>>> +#define READBACK_NEGATE                BIT(0)
>>> I confirm that this change is technically correct. It fixes a bug.
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diff mbox

Patch

diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c
index 74ea5765938b..136975220c92 100644
--- a/drivers/thermal/tegra_soctherm.c
+++ b/drivers/thermal/tegra_soctherm.c
@@ -57,7 +57,7 @@ 
 #define READBACK_VALUE_MASK			0xff00
 #define READBACK_VALUE_SHIFT			8
 #define READBACK_ADD_HALF			BIT(7)
-#define READBACK_NEGATE				BIT(1)
+#define READBACK_NEGATE				BIT(0)
 
 #define FUSE_TSENSOR8_CALIB			0x180
 #define FUSE_SPARE_REALIGNMENT_REG_0		0x1fc