| Message ID | 1456441583-20932-5-git-send-email-stuart.yoder@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
Hi Stuart, Please see my comments inline. Thanks, Minghuan > -----Original Message----- > From: Stuart Yoder [mailto:stuart.yoder@nxp.com] > Sent: Friday, February 26, 2016 7:06 AM > To: u-boot@lists.denx.de > Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; > Minghuan Lian <minghuan.lian@nxp.com>; Yang-Leo Li <leoyang.li@nxp.com>; > marc.zyngier@arm.com; Stuart Yoder <stuart.yoder@nxp.com> > Subject: [PATCH 4/7 v2] pci/layerscape: add support for LUT > > From: Stuart Yoder <stuart.yoder@nxp.com> > > The per-PCI controller LUT (Look-Up-Table) is a 32-entry table > that maps PCI requester IDs (bus/dev/fun) to a stream ID. > > This patch implements infrastructure to enable LUT initialization: > -define registers offsets > -add an index to 'struct ls_pcie' to track next available slot in LUT > -add function to allocate the next available entry index > -add function to program a LUT entry > > Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> > --- > -v2 > -no changes > > drivers/pci/pcie_layerscape.c | 36 > ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c > index bb29222..6886488 100644 > --- a/drivers/pci/pcie_layerscape.c > +++ b/drivers/pci/pcie_layerscape.c > @@ -58,6 +58,13 @@ > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > #define PCIE_ATU_UPPER_TARGET 0x91C > > +/* LUT registers */ > +#define PCIE_LUT_BASE 0x80000 [Minghuan Lian] PCIE_LUT_BASE has been defined in immap_lsch2.h and immap_lsch3.h. LS1043a has the different base address. > +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) > +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) > +#define PCIE_LUT_ENABLE (1 << 31) > +#define PCIE_LUT_ENTRY_COUNT 32 > + > #define PCIE_DBI_RO_WR_EN 0x8bc > > #define PCIE_LINK_CAP 0x7c > @@ -93,6 +100,7 @@ struct ls_pcie { > void __iomem *dbi; > void __iomem *va_cfg0; > void __iomem *va_cfg1; > + int next_lut_index; > struct pci_controller hose; > }; > > @@ -482,6 +490,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, > struct ls_pcie_info *info) > } > } > > + > +/* > + * Return next available LUT index. > + */ > +static u32 ls_pcie_next_lut_index(struct ls_pcie *pcie) > +{ > + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) > + return pcie->next_lut_index++; > + else > + return -1; /* LUT is full */ > +} > + > +/* > + * Program a single LUT entry > + */ > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, > + u32 streamid) > +{ > + void __iomem *lut; > + > + lut = pcie->dbi + PCIE_LUT_BASE; > + > + /* leave mask as all zeroes, want to match all bits */ > + writel((devid << 16), lut + PCIE_LUT_UDR(index)); > + writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); > +} > + > int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) > { > struct ls_pcie *pcie; > @@ -513,6 +548,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, > struct ls_pcie_info *info) > pcie->va_cfg1 = map_physmem(info->cfg1_phys, > info->cfg1_size, > MAP_NOCACHE); > + pcie->next_lut_index = 0; > > /* outbound memory */ > pci_set_region(&hose->regions[0], > -- > 1.7.9.5
> -----Original Message----- > From: Minghuan Lian > Sent: Thursday, February 25, 2016 11:56 PM > To: Stuart Yoder <stuart.yoder@nxp.com>; u-boot@lists.denx.de > Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; > Mingkai Hu <mingkai.hu@nxp.com>; Yang-Leo Li <leoyang.li@nxp.com>; marc.zyngier@arm.com; > Stuart Yoder <stuart.yoder@nxp.com> > Subject: RE: [PATCH 4/7 v2] pci/layerscape: add support for LUT > > Hi Stuart, > > Please see my comments inline. > > Thanks, > Minghuan > > > -----Original Message----- > > From: Stuart Yoder [mailto:stuart.yoder@nxp.com] > > Sent: Friday, February 26, 2016 7:06 AM > > To: u-boot@lists.denx.de > > Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha > > <prabhakar.kushwaha@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; > > Minghuan Lian <minghuan.lian@nxp.com>; Yang-Leo Li <leoyang.li@nxp.com>; > > marc.zyngier@arm.com; Stuart Yoder <stuart.yoder@nxp.com> > > Subject: [PATCH 4/7 v2] pci/layerscape: add support for LUT > > > > From: Stuart Yoder <stuart.yoder@nxp.com> > > > > The per-PCI controller LUT (Look-Up-Table) is a 32-entry table > > that maps PCI requester IDs (bus/dev/fun) to a stream ID. > > > > This patch implements infrastructure to enable LUT initialization: > > -define registers offsets > > -add an index to 'struct ls_pcie' to track next available slot in LUT > > -add function to allocate the next available entry index > > -add function to program a LUT entry > > > > Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> > > --- > > -v2 > > -no changes > > > > drivers/pci/pcie_layerscape.c | 36 > > ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 36 insertions(+) > > > > diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c > > index bb29222..6886488 100644 > > --- a/drivers/pci/pcie_layerscape.c > > +++ b/drivers/pci/pcie_layerscape.c > > @@ -58,6 +58,13 @@ > > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > > #define PCIE_ATU_UPPER_TARGET 0x91C > > > > +/* LUT registers */ > > +#define PCIE_LUT_BASE 0x80000 > [Minghuan Lian] PCIE_LUT_BASE has been defined in immap_lsch2.h and immap_lsch3.h. > LS1043a has the different base address. > > > +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) > > +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) > > +#define PCIE_LUT_ENABLE (1 << 31) > > +#define PCIE_LUT_ENTRY_COUNT 32 > > + I'll move the new defines into immap_lsch3.h. Stuart
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index bb29222..6886488 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -58,6 +58,13 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_ENABLE (1 << 31) +#define PCIE_LUT_ENTRY_COUNT 32 + #define PCIE_DBI_RO_WR_EN 0x8bc #define PCIE_LINK_CAP 0x7c @@ -93,6 +100,7 @@ struct ls_pcie { void __iomem *dbi; void __iomem *va_cfg0; void __iomem *va_cfg1; + int next_lut_index; struct pci_controller hose; }; @@ -482,6 +490,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) } } + +/* + * Return next available LUT index. + */ +static u32 ls_pcie_next_lut_index(struct ls_pcie *pcie) +{ + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) + return pcie->next_lut_index++; + else + return -1; /* LUT is full */ +} + +/* + * Program a single LUT entry + */ +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, + u32 streamid) +{ + void __iomem *lut; + + lut = pcie->dbi + PCIE_LUT_BASE; + + /* leave mask as all zeroes, want to match all bits */ + writel((devid << 16), lut + PCIE_LUT_UDR(index)); + writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); +} + int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) { struct ls_pcie *pcie; @@ -513,6 +548,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) pcie->va_cfg1 = map_physmem(info->cfg1_phys, info->cfg1_size, MAP_NOCACHE); + pcie->next_lut_index = 0; /* outbound memory */ pci_set_region(&hose->regions[0],