From patchwork Mon Jul 12 18:41:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 58657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2FB08B6EF3 for ; Tue, 13 Jul 2010 05:07:39 +1000 (EST) Received: from localhost ([127.0.0.1]:51389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OYOLo-0002ig-8Q for incoming@patchwork.ozlabs.org; Mon, 12 Jul 2010 15:07:36 -0400 Received: from [140.186.70.92] (port=35920 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OYO2d-0005XX-9P for qemu-devel@nongnu.org; Mon, 12 Jul 2010 14:47:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OYO2b-0007Db-Kh for qemu-devel@nongnu.org; Mon, 12 Jul 2010 14:47:46 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:40564) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OYO2b-0007DR-AP for qemu-devel@nongnu.org; Mon, 12 Jul 2010 14:47:45 -0400 Received: by pwi2 with SMTP id 2so1973620pwi.4 for ; Mon, 12 Jul 2010 11:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:from:date :message-id:subject:to:content-type; bh=Iir0lB3bnOACUMrO2uuoS3xsU0HBihgrSzySQx1QZcc=; b=KoK9eFKiH1WRylFFNpjEPAPPG7j+HV74m8DQCrPLOp3AEA4O/zu3hg+9DeS9GTm0zV B/O8Np/YuIxbGlwUOKi/rCU3EsHnjoGQh4Pvlu9mqVF6Ht32GSrBhEOwMB2LbH83Zu/H 24k0MiGY566FyqxH4m5IXRBb8UwxiTCNYkLeA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; b=M8pf4p32AdqDLPapx3Roy/c2MbCdw5iye9U7jedBoqVCm88A+Bf2ZJhsxDy4G3B7J0 2Wg7FMKuW6UJgZUAPu0Q6sSTsR3VmjWY9IAnz9UJVkO2Nw72Y4p1g1RP3oRFyz5z3Fph IxrI7UbW+fmBz5zxiZ1yPOsPfMj79FOrlwmE0= Received: by 10.142.177.21 with SMTP id z21mr13822226wfe.73.1278960101152; Mon, 12 Jul 2010 11:41:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.212.14 with HTTP; Mon, 12 Jul 2010 11:41:21 -0700 (PDT) From: Blue Swirl Date: Mon, 12 Jul 2010 18:41:21 +0000 Message-ID: To: qemu-devel , Anthony Liguori , "Michael S. Tsirkin" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: Subject: [Qemu-devel] [PATCH 09/15] cmd646: convert to pci_bar_map X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use pci_bar_map() instead of a mapping function. Signed-off-by: Blue Swirl --- hw/ide/cmd646.c | 149 ++++++++++++++++++++++++++++++++++--------------------- 1 files changed, 92 insertions(+), 57 deletions(-) registers */ @@ -232,6 +238,8 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); uint8_t *pci_conf = d->dev.config; qemu_irq *irq; + unsigned int i; + int io_index; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); @@ -247,11 +255,38 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) pci_conf[0x51] |= 0x08; /* enable IDE1 */ } - pci_register_bar(dev, 0, 0x8, PCI_BASE_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 1, 0x4, PCI_BASE_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 2, 0x8, PCI_BASE_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 3, 0x4, PCI_BASE_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map); + pci_register_bar(dev, 0, 8, PCI_BASE_ADDRESS_SPACE_IO, NULL); + io_index = cpu_register_io(ide_ioport_reads, ide_ioport_writes, 8, &d->bus[0]); + pci_bar_map(&d->dev, 0, 0, 0, 8, io_index); + pci_register_bar(dev, 1, 4, PCI_BASE_ADDRESS_SPACE_IO, NULL); + io_index = cpu_register_io(ide_status_reads, ide_cmd_writes, 1, &d->bus[0]); + pci_bar_map(&d->dev, 1, 0, 2, 1, io_index); + pci_register_bar(dev, 2, 8, PCI_BASE_ADDRESS_SPACE_IO, NULL); + io_index = cpu_register_io(ide_ioport_reads, ide_ioport_writes, 8, &d->bus[1]); + pci_bar_map(&d->dev, 2, 0, 0, 8, io_index); + pci_register_bar(dev, 3, 4, PCI_BASE_ADDRESS_SPACE_IO, NULL); + io_index = cpu_register_io(ide_status_reads, ide_cmd_writes, 1, &d->bus[1]); + pci_bar_map(&d->dev, 3, 0, 2, 1, io_index); + pci_register_bar(dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, NULL); + for (i = 0; i < 2; i++) { + BMDMAState *bm = &d->bmdma[i]; + + d->bus[i].bmdma = bm; + bm->bus = d->bus+i; + qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); + + if (i == 0) { + io_index = cpu_register_io(bmdma_io_reads_0, bmdma_io_writes_0, + 1, d); + } else { + io_index = cpu_register_io(bmdma_io_reads_1, bmdma_io_writes_1, + 1, d); + } + pci_bar_map(&d->dev, 4, i * 2 + 0, i * 8 + 0, 1, io_index); + + io_index = cpu_register_io(bmdma_addr_reads, bmdma_addr_writes, 4, bm); + pci_bar_map(&d->dev, 4, i * 2 + 1, i * 8 + 4, 4, io_index); + } /* TODO: RST# value should be 0 */ pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index ff80dd5..ec080e0 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -44,29 +44,29 @@ static void cmd646_update_irq(PCIIDEState *d); -static void ide_map(PCIDevice *pci_dev, int region_num, - pcibus_t addr, pcibus_t size, int type) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); - IDEBus *bus; - - if (region_num <= 3) { - bus = &d->bus[(region_num >> 1)]; - if (region_num & 1) { - register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); - register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); - } else { - register_ioport_write(addr, 8, 1, ide_ioport_write, bus); - register_ioport_read(addr, 8, 1, ide_ioport_read, bus); - - /* data ports */ - register_ioport_write(addr, 2, 2, ide_data_writew, bus); - register_ioport_read(addr, 2, 2, ide_data_readw, bus); - register_ioport_write(addr, 4, 4, ide_data_writel, bus); - register_ioport_read(addr, 4, 4, ide_data_readl, bus); - } - } -} +static IOPortWriteFunc * const ide_cmd_writes[] = { + ide_cmd_write, + NULL, + NULL, +}; + +static IOPortReadFunc * const ide_status_reads[] = { + ide_status_read, + NULL, + NULL, +}; + +static IOPortWriteFunc * const ide_ioport_writes[] = { + ide_ioport_write, + ide_data_writew, + ide_data_writel, +}; + +static IOPortReadFunc * const ide_ioport_reads[] = { + ide_ioport_read, + ide_data_readw, + ide_data_readl, +}; static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm, uint32_t addr) @@ -159,35 +159,41 @@ static void bmdma_writeb_1(void *opaque, uint32_t addr, uint32_t val) bmdma_writeb_common(pci_dev, bm, addr, val); } -static void bmdma_map(PCIDevice *pci_dev, int region_num, - pcibus_t addr, pcibus_t size, int type) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); - int i; +static IOPortWriteFunc * const bmdma_io_writes_0[] = { + bmdma_writeb_0, + NULL, + NULL, +}; - for(i = 0;i < 2; i++) { - BMDMAState *bm = &d->bmdma[i]; - d->bus[i].bmdma = bm; - bm->bus = d->bus+i; - qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); +static IOPortReadFunc * const bmdma_io_reads_0[] = { + bmdma_readb_0, + NULL, + NULL, +}; - if (i == 0) { - register_ioport_write(addr, 4, 1, bmdma_writeb_0, d); - register_ioport_read(addr, 4, 1, bmdma_readb_0, d); - } else { - register_ioport_write(addr, 4, 1, bmdma_writeb_1, d); - register_ioport_read(addr, 4, 1, bmdma_readb_1, d); - } +static IOPortWriteFunc * const bmdma_io_writes_1[] = { + bmdma_writeb_1, + NULL, + NULL, +}; - register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); - register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); - register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); - register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); - register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); - register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); - addr += 8; - } -} +static IOPortReadFunc * const bmdma_io_reads_1[] = { + bmdma_readb_1, + NULL, + NULL, +}; + +static IOPortWriteFunc * const bmdma_addr_writes[] = { + bmdma_addr_writeb, + bmdma_addr_writew, + bmdma_addr_writel, +}; + +static IOPortReadFunc * const bmdma_addr_reads[] = { + bmdma_addr_readb, + bmdma_addr_readw, + bmdma_addr_readl, +}; /* XXX: call it also when the MRDMODE is changed from the PCI config