Patchwork [5/5] mtd/nand/denali.c: remove set_ecc_config functions

login
register
mail settings
Submitter Dong, Chuanxiao
Date July 12, 2010, 9:04 a.m.
Message ID <5D8008F58939784290FAB48F549751981D09B718B7@shsmsx502.ccr.corp.intel.com>
Download mbox | patch
Permalink /patch/58601/
State New
Headers show

Comments

Dong, Chuanxiao - July 12, 2010, 9:04 a.m.
From 399e22e9f1bc32558961391db377309b08806b25 Mon Sep 17 00:00:00 2001
From: Chuanxiao Dong <chuanxiao.dong@intel.com>
Date: Mon, 21 Jun 2010 18:51:19 +0800
Subject: [PATCH 5/5] [MTD/denali] remove set_ecc_config
 	This function only need to set ECC_CORRECTION reg
 	so remove it and set this reg in probe function.
 	For denali nand controller only support 15bits and
 	8bits ecc correction on MRST, here use 15bits ecc
 	correction for MLC NAND and 8bits ecc correction for
 	SLC NAND.

Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
---
 drivers/mtd/nand/denali.c |   44 ++------------------------------------------
 1 files changed, 2 insertions(+), 42 deletions(-)

Patch

diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 1555921..d143b0b 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -354,46 +354,6 @@  static void nand_onfi_timing_set(struct denali_nand_info *denali,
 	denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
 }
 
-/* configures the initial ECC settings for the controller */
-static void set_ecc_config(struct denali_nand_info *denali)
-{
-#if SUPPORT_8BITECC
-	if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
-		(ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
-		denali_write32(8, denali->flash_reg + ECC_CORRECTION);
-#endif
-
-	if ((ioread32(denali->flash_reg + ECC_CORRECTION) &
-				ECC_CORRECTION__VALUE) == 1) {
-		denali->dev_info.wECCBytesPerSector = 4;
-		denali->dev_info.wECCBytesPerSector *=
-			denali->dev_info.wDevicesConnected;
-		denali->dev_info.wNumPageSpareFlag =
-			denali->dev_info.wPageSpareSize -
-			denali->dev_info.wPageDataSize /
-			(ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
-			denali->dev_info.wECCBytesPerSector
-			- denali->dev_info.wSpareSkipBytes;
-	} else {
-		denali->dev_info.wECCBytesPerSector =
-			(ioread32(denali->flash_reg + ECC_CORRECTION) &
-			ECC_CORRECTION__VALUE) * 13 / 8;
-		if ((denali->dev_info.wECCBytesPerSector) % 2 == 0)
-			denali->dev_info.wECCBytesPerSector += 2;
-		else
-			denali->dev_info.wECCBytesPerSector += 1;
-
-		denali->dev_info.wECCBytesPerSector *=
-			denali->dev_info.wDevicesConnected;
-		denali->dev_info.wNumPageSpareFlag =
-			denali->dev_info.wPageSpareSize -
-			denali->dev_info.wPageDataSize /
-			(ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
-			denali->dev_info.wECCBytesPerSector
-			- denali->dev_info.wSpareSkipBytes;
-	}
-}
-
 /* queries the NAND device to see what ONFI modes it supports. */
 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
 {
@@ -900,8 +860,6 @@  static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
 	denali->dev_info.nBitsInBlockDataSize =
 		ilog2(denali->dev_info.wBlockDataSize);
 
-	set_ecc_config(denali);
-
 	no_of_planes = ioread32(denali->flash_reg + NUMBER_OF_PLANES) &
 		NUMBER_OF_PLANES__VALUE;
 
@@ -2075,9 +2033,11 @@  static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	if (denali->dev_info.MLCDevice) {
 		denali->nand.ecc.layout = &nand_oob_mlc_14bit;
 		denali->nand.ecc.bytes = ECC_BYTES_MLC;
+		denali_write32(15, denali->flash_reg + ECC_CORRECTION);
 	} else { /* SLC */
 		denali->nand.ecc.layout = &nand_oob_slc;
 		denali->nand.ecc.bytes = ECC_BYTES_SLC;
+		denali_write32(8, denali->flash_reg + ECC_CORRECTION);
 	}
 
 	/* These functions are required by the NAND core framework, otherwise,