| Message ID | 1455906029-25565-4-git-send-email-somlo@cmu.edu |
|---|---|
| State | New |
| Headers | show |
On Fri, 19 Feb 2016 13:20:27 -0500 "Gabriel L. Somlo" <somlo@cmu.edu> wrote: > Add a fw_cfg device node to the ACPI DSDT. While the guest-side > firmware can't utilize this information (since it has to access > the hard-coded fw_cfg device to extract ACPI tables to begin with), > having fw_cfg listed in ACPI will help the guest kernel keep a more > accurate inventory of in-use IO port regions. > > Signed-off-by: Gabriel Somlo <somlo@cmu.edu> > Reviewed-by: Laszlo Ersek <lersek@redhat.com> > Reviewed-by: Marc Marí <markmb@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> > --- > hw/i386/acpi-build.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 4554eb8..915fddd 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -2190,6 +2190,35 @@ build_dsdt(GArray *table_data, GArray *linker, > aml_append(scope, aml_name_decl("_S5", pkg)); > aml_append(dsdt, scope); > > + /* create fw_cfg node, unconditionally */ > + { > + /* when using port i/o, the 8-bit data register *always* overlaps > + * with half of the 16-bit control register. Hence, the total size > + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the > + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ > + uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), > + "dma_enabled", NULL) ? > + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : > + FW_CFG_CTL_SIZE; > + > + scope = aml_scope("\\_SB.PCI0"); > + dev = aml_device("FWCF"); > + > + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); > + > + /* device present, functioning, decoding, not shown in UI */ > + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); > + > + crs = aml_resource_template(); > + aml_append(crs, > + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) > + ); > + aml_append(dev, aml_name_decl("_CRS", crs)); > + > + aml_append(scope, dev); > + aml_append(dsdt, scope); > + } > + > if (misc->applesmc_io_base) { > scope = aml_scope("\\_SB.PCI0.ISA"); > dev = aml_device("SMC");
On Fri, Feb 19, 2016 at 01:20:27PM -0500, Gabriel L. Somlo wrote: > Add a fw_cfg device node to the ACPI DSDT. While the guest-side > firmware can't utilize this information (since it has to access > the hard-coded fw_cfg device to extract ACPI tables to begin with), > having fw_cfg listed in ACPI will help the guest kernel keep a more > accurate inventory of in-use IO port regions. > > Signed-off-by: Gabriel Somlo <somlo@cmu.edu> > Reviewed-by: Laszlo Ersek <lersek@redhat.com> > Reviewed-by: Marc Marí <markmb@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> > --- > hw/i386/acpi-build.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 4554eb8..915fddd 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -2190,6 +2190,35 @@ build_dsdt(GArray *table_data, GArray *linker, > aml_append(scope, aml_name_decl("_S5", pkg)); > aml_append(dsdt, scope); > > + /* create fw_cfg node, unconditionally */ > + { > + /* when using port i/o, the 8-bit data register *always* overlaps > + * with half of the 16-bit control register. Hence, the total size > + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the > + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ > + uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), > + "dma_enabled", NULL) ? > + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : > + FW_CFG_CTL_SIZE; > + > + scope = aml_scope("\\_SB.PCI0"); > + dev = aml_device("FWCF"); > + > + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); > + > + /* device present, functioning, decoding, not shown in UI */ > + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); > + > + crs = aml_resource_template(); > + aml_append(crs, > + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) > + ); > + aml_append(dev, aml_name_decl("_CRS", crs)); > + > + aml_append(scope, dev); > + aml_append(dsdt, scope); > + } > + > if (misc->applesmc_io_base) { > scope = aml_scope("\\_SB.PCI0.ISA"); > dev = aml_device("SMC"); > -- > 2.4.3
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4554eb8..915fddd 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2190,6 +2190,35 @@ build_dsdt(GArray *table_data, GArray *linker, aml_append(scope, aml_name_decl("_S5", pkg)); aml_append(dsdt, scope); + /* create fw_cfg node, unconditionally */ + { + /* when using port i/o, the 8-bit data register *always* overlaps + * with half of the 16-bit control register. Hence, the total size + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ + uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), + "dma_enabled", NULL) ? + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : + FW_CFG_CTL_SIZE; + + scope = aml_scope("\\_SB.PCI0"); + dev = aml_device("FWCF"); + + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); + + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + + crs = aml_resource_template(); + aml_append(crs, + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) + ); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + aml_append(dsdt, scope); + } + if (misc->applesmc_io_base) { scope = aml_scope("\\_SB.PCI0.ISA"); dev = aml_device("SMC");