===================================================================
@@ -13,6 +13,10 @@
* config/arm/arm.md (Thumb-1 ldrsb peephole): New.
+ * config/arm/arm.md (cbranchqi4): Fix array size.
+ (addsi3_cbranch): Also andle alternative 2 like alternative 3 when
+ calculating length.
+
2010-07-09 Richard Guenther <rguenther@suse.de>
* gimple.c (struct type_fixup_s): New struct and VEC type.
===================================================================
@@ -6562,7 +6562,7 @@ (define_expand "cbranchqi4"
(pc)))]
"TARGET_THUMB1"
{
- rtx xops[3];
+ rtx xops[4];
xops[1] = gen_reg_rtx (SImode);
emit_insn (gen_zero_extendqisi2 (xops[1], operands[1]));
xops[2] = GEN_INT (127);
@@ -7509,7 +7509,7 @@ (define_insn "*addsi3_cbranch"
else if (which_alternative >= 4)
output_asm_insn (\"str\\t%1, %0\", operands);
- switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0))
+ switch (get_attr_length (insn) - ((which_alternative >= 2) ? 2 : 0))
{
case 4:
return \"b%d4\\t%l5\";
@@ -7523,7 +7523,7 @@ (define_insn "*addsi3_cbranch"
[(set (attr "far_jump")
(if_then_else
(ior (and (lt (symbol_ref ("which_alternative"))
- (const_int 3))
+ (const_int 2))
(eq_attr "length" "8"))
(eq_attr "length" "10"))
(const_string "yes")
@@ -7531,7 +7531,7 @@ (define_insn "*addsi3_cbranch"
(set (attr "length")
(if_then_else
(lt (symbol_ref ("which_alternative"))
- (const_int 3))
+ (const_int 2))
(if_then_else
(and (ge (minus (match_dup 5) (pc)) (const_int -250))
(le (minus (match_dup 5) (pc)) (const_int 256)))
This patch fixes two problems introduced by some of my earlier changes. In addsi3_cbranch, I had changed alternative 2 to emit an extra move instruction like the higher-numbered alternatives, but forgot to update insn length calculations. In cbranchqi4, the array size was too small. Regression tested as usual with qemu-system-armv7/arch=armv7-a/thumb qemu-system-armv7/thumb qemu-system-armv7 and committed as obvious. Bernd