From patchwork Fri Jul 9 10:10:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 58382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5112EB6EFE for ; Fri, 9 Jul 2010 20:11:50 +1000 (EST) Received: (qmail 4982 invoked by alias); 9 Jul 2010 10:11:48 -0000 Received: (qmail 4962 invoked by uid 22791); 9 Jul 2010 10:11:46 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 09 Jul 2010 10:11:38 +0000 Received: (qmail 26182 invoked from network); 9 Jul 2010 10:11:36 -0000 Received: from unknown (HELO ?84.152.202.138?) (bernds@127.0.0.2) by mail.codesourcery.com with ESMTPA; 9 Jul 2010 10:11:36 -0000 Message-ID: <4C36F592.6040901@codesourcery.com> Date: Fri, 09 Jul 2010 12:10:26 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100625 Thunderbird/3.0.5 MIME-Version: 1.0 To: GCC Patches CC: Richard Earnshaw Subject: ARM patch: Add a Thumb-1 ldrsb peephole Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Here's a small by-product of my attempts to tune Thumb-1 code. - add r3, r3, #124 - mov r7, #0 + mov r7, #124 ldrsb r7, [r3, r7] Tested in the same run as mentioned in http://gcc.gnu.org/ml/gcc-patches/2010-07/msg00756.html Ok? Bernd * config/arm/arm.md (Thumb-1 ldrsb peephole): New. Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 161987) +++ config/arm/arm.md (working copy) @@ -4619,6 +4619,27 @@ (define_split operands[3] = change_address (operands[1], QImode, addr); }) +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_dup 0) (match_operand 1 "const_int_operand"))) + (set (match_operand:SI 2 "register_operand" "") (const_int 0)) + (set (match_operand:SI 3 "register_operand" "") + (sign_extend:SI (match_operand:QI 4 "memory_operand" "")))] + "TARGET_THUMB1 + && GET_CODE (XEXP (operands[4], 0)) == PLUS + && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0)) + && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1)) + && (peep2_reg_dead_p (3, operands[0]) + || rtx_equal_p (operands[0], operands[3])) + && (peep2_reg_dead_p (3, operands[2]) + || rtx_equal_p (operands[2], operands[3]))" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 3) (sign_extend:SI (match_dup 4)))] +{ + rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]); + operands[4] = change_address (operands[4], QImode, addr); +}) + (define_insn "thumb1_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=l,l,l") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]