From patchwork Fri Jul  9 08:39:55 2010
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Subject: [vect] Ask for review and approving the patch about vect and loongson
Date: Thu, 08 Jul 2010 22:39:55 -0000
From: Eric Fisher <joefoxreal@gmail.com>
X-Patchwork-Id: 58374
Message-Id: <AANLkTinqFduvYYgBpemJpRJDR1q2T1hECpKcEcIxAZAL@mail.gmail.com>
To: Richard Guenther <richard.guenther@gmail.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>

2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
>
> How about splitting the patch?
>
> Richard.
>

Thanks. I put the patch separately now. And the ChageLogs,

gcc/ChangeLog
  * sourcebuild.texi: Remove duplicated item vect_int_mult.
  * loongson.md: Add define_expand for standard names mulm3 (VH),
ashrm3 (VWH), lshrm3 (VWH) to generate SIMD automatically.

testsuite/ChangeLog
  * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
  * vect.exp: Go on running the testsuite when the target is mips*
  * target-supports.exp: Check loongson target in vector specific attributes.


Thanks,
Eric


Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 161865)
+++ config/mips/loongson.md	(working copy)
@@ -352,6 +352,16 @@
   "pmulh<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern mulm3
+(define_expand "mul<mode>3"
+  [(set (match_operand:VH 0 "register_operand" "=f")
+        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
+                    (match_operand:VH 2 "register_operand" "f")]
+                   UNSPEC_LOONGSON_PMULL))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
+
 ;; Multiply signed integers and store low result.
 (define_insn "loongson_pmull<V_suffix>"
   [(set (match_operand:VH 0 "register_operand" "=f")
@@ -421,6 +431,14 @@
   "psll<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern ashrm3
+(define_expand "ashr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right arithmetic.
 (define_insn "loongson_psra<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")
@@ -430,6 +448,14 @@
   "psra<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
 
+;; Standard pattern lshrm3
+(define_expand "lshr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right logical.
 (define_insn "loongson_psrl<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")