@@ -19,5 +19,5 @@ CONFIG_TARGET_ALT=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -21,6 +21,6 @@ CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_DM_SPI=y
CONFIG_MTD=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
@@ -8,7 +8,7 @@ CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
@@ -18,5 +18,5 @@ CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SYS_NS16550=y
@@ -6,5 +6,5 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -17,7 +17,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
@@ -15,7 +15,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
@@ -11,7 +11,7 @@ CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
@@ -10,7 +10,7 @@ CONFIG_SPL=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
@@ -19,5 +19,5 @@ CONFIG_TARGET_GOSE=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -19,5 +19,5 @@ CONFIG_TARGET_KOELSCH=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -19,5 +19,5 @@ CONFIG_TARGET_LAGER=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -10,7 +10,7 @@ CONFIG_SPL=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -8,5 +8,5 @@ CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -8,4 +8,4 @@ CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
@@ -19,5 +19,5 @@ CONFIG_TARGET_PORTER=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -19,5 +19,5 @@ CONFIG_TARGET_SILK=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -19,5 +19,5 @@ CONFIG_TARGET_STOUT=y
CONFIG_SH_SDHI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -14,7 +14,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -15,7 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -16,7 +16,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
@@ -16,5 +16,5 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_ZYNQ_GEM=y
@@ -15,7 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_NOR_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -22,7 +22,7 @@ Commands to erase/write u-boot/mlo to flash device
--------------------------------------------------
U-Boot# sf probe 0
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
-SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR
+SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_NOR_BAR
U-Boot# sf erase 0 0x10000
SF: 65536 bytes @ 0x0 Erased: OK
U-Boot# sf erase 0x20000 0x10000
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SEQID_PP 6
#define SEQID_RDID 7
#define SEQID_BE_4K 8
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
#define SEQID_BRRD 9
#define SEQID_BRWR 10
#define SEQID_RDEAR 11
@@ -178,7 +178,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
qspi_write32(priv->flags, ®s->lut[lut_base],
OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
@@ -214,7 +214,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
/* Erase a sector */
lut_base = SEQID_SE * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
@@ -245,7 +245,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
/* Page Program */
lut_base = SEQID_PP * 4;
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
@@ -291,7 +291,7 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
/*
* BRRD BRWR RDEAR WREAR are all supported, because it is hard to
* dynamically check whether to set BRRD BRWR or RDEAR WREAR during
@@ -430,7 +430,7 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
}
#endif
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
/* Bank register read/write, EAR register read/write */
static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
{
@@ -601,7 +601,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
/* Default is page programming */
seqid = SEQID_PP;
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
if (priv->cur_seqid == QSPI_CMD_BRWR)
seqid = SEQID_BRWR;
else if (priv->cur_seqid == QSPI_CMD_WREAR)
@@ -735,7 +735,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
(priv->cur_seqid == QSPI_CMD_WREAR)) {
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
wr_sfaddr = 0;
#endif
}
@@ -752,7 +752,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
qspi_op_rdid(priv, din, bytes);
else if (priv->cur_seqid == QSPI_CMD_RDSR)
qspi_op_rdsr(priv, din, bytes);
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
(priv->cur_seqid == QSPI_CMD_RDEAR)) {
priv->sf_addr = 0;
@@ -583,7 +583,7 @@ unsigned long get_board_ddr_clk(void);
#ifndef CONFIG_SPL_BUILD
#endif
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -573,7 +573,7 @@ unsigned long get_board_ddr_clk(void);
#elif defined(CONFIG_T1023RDB)
#endif
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -537,7 +537,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -554,7 +554,7 @@ unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#endif
@@ -504,7 +504,7 @@ unsigned long get_board_ddr_clk(void);
* eSPI - Enhanced SPI
*/
#ifdef CONFIG_MTD_SPI_NOR
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -69,7 +69,7 @@
#ifdef CONFIG_CMD_SF
#define CONFIG_MXC_SPI
#define CONFIG_SPI_FLASH_MTD
- #define CONFIG_SPI_FLASH_BAR
+ #define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
/* GPIO 3-19 (21248) */
@@ -296,7 +296,7 @@ int get_scl(void);
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
+#define CONFIG_SPI_NOR_BAR /* 4 byte-addressing */
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -259,7 +259,7 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_CMD_SF
#define CONFIG_MTD_SPI_NOR
#define CONFIG_MTD_M25P80
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#endif
/*
@@ -199,7 +199,7 @@
#define CONFIG_CMD_SF
#define CONFIG_MTD_SPI_NOR
#define CONFIG_MTD_M25P80
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
@@ -266,7 +266,7 @@
#define CONFIG_MTD_SPI_NOR
#define CONFIG_MTD_M25P80
#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
@@ -92,7 +92,7 @@
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
/*
* The base address is configurable in QSys, each board must specify the
* base address based on it's particular FPGA configuration. Please note
@@ -218,7 +218,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_NOR_BAR
/*
* Designware SPI support
@@ -205,7 +205,7 @@ struct spi_nor {
u8 read_opcode;
u8 read_dummy;
u8 program_opcode;
-#ifdef CONFIG_SPI_FLASH_BAR
+#ifdef CONFIG_SPI_NOR_BAR
u8 bar_read_opcode;
u8 bar_program_opcode;
u8 bank_curr;
CONFIG_SPI_FLASH_BAR => CONFIG_SPI_NOR_BAR Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com> --- configs/alt_defconfig | 2 +- configs/am437x_sk_evm_defconfig | 2 +- configs/am43xx_evm_defconfig | 2 +- configs/am57xx_evm_defconfig | 2 +- configs/bg0900_defconfig | 2 +- configs/dra72_evm_defconfig | 2 +- configs/dra74_evm_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/ds414_defconfig | 2 +- configs/gose_defconfig | 2 +- configs/koelsch_defconfig | 2 +- configs/lager_defconfig | 2 +- configs/maxbcm_defconfig | 2 +- configs/mx6sxsabreauto_defconfig | 2 +- configs/mx6sxsabresd_defconfig | 2 +- configs/porter_defconfig | 2 +- configs/silk_defconfig | 2 +- configs/stout_defconfig | 2 +- configs/zynq_zc702_defconfig | 2 +- configs/zynq_zc706_defconfig | 2 +- configs/zynq_zc770_xm010_defconfig | 2 +- configs/zynq_zc770_xm013_defconfig | 2 +- configs/zynq_zed_defconfig | 2 +- doc/SPI/README.ti_qspi_dra_test | 2 +- drivers/spi/fsl_qspi.c | 18 +++++++++--------- include/configs/T102xQDS.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/ls2080ardb.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/socfpga_common.h | 4 ++-- include/linux/mtd/spi-nor.h | 2 +- 37 files changed, 46 insertions(+), 46 deletions(-)