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[U-Boot,v4,10/14] crypto/fsl: Correct 64bit Write when MMU disabled

Message ID 1454995422-31731-11-git-send-email-saksham.jain@nxp.com
State Changes Requested
Delegated to: York Sun
Headers show

Commit Message

Saksham Jain Feb. 9, 2016, 5:23 a.m. UTC 
When MMU is disabled, 64bit Write must be at a memory aligned at
64bit Boundary. So, this commit splits the 64bit write into 2 -32bit
writes as the memory location is not guaranteed to be 64bit aligned.
The alignment exception only occurs when MMU is disabled.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
---
Changes for v2:
	- No changes
Changes for v3:
	- No changes
Changes for v4:
	- No changes

 drivers/crypto/fsl/desc_constr.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

York Sun March 18, 2016, 3:58 p.m. UTC | #1 
On 02/08/2016 09:27 PM, Saksham Jain wrote:
> When MMU is disabled, 64bit Write must be at a memory aligned at
> 64bit Boundary. So, this commit splits the 64bit write into 2 -32bit

s/-32bit/32-bit

or you can use 32bit for consistency.

> writes as the memory location is not guaranteed to be 64bit aligned.
> The alignment exception only occurs when MMU is disabled.
> 


York
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Patch

diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index 2559ccd..db6ddee 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -85,10 +85,9 @@  static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 #ifdef CONFIG_PHYS_64BIT
 	/* The Position of low and high part of 64 bit address
 	 * will depend on the endianness of CAAM Block */
-	union ptr_addr_t ptr_addr;
-	ptr_addr.m_halfs.high = (u32)(ptr >> 32);
-	ptr_addr.m_halfs.low = (u32)ptr;
-	*offset = ptr_addr.m_whole;
+	union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+	ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+	ptr_addr->m_halfs.low = (u32)ptr;
 #else
 	*offset = ptr;
 #endif