Index: testsuite/gcc.c-torture/compile/pr44788.c
===================================================================
--- testsuite/gcc.c-torture/compile/pr44788.c	(revision 0)
+++ testsuite/gcc.c-torture/compile/pr44788.c	(revision 0)
@@ -0,0 +1,8 @@
+void joint_decode(float* mlt_buffer1, int t) {
+    int i;
+    float decode_buffer[1060];
+    foo(decode_buffer);
+    for (i=0; i<10 ; i++) {
+        mlt_buffer1[i] = i * decode_buffer[t];
+    }
+}
Index: testsuite/gcc.target/arm/pr44788.c
===================================================================
--- testsuite/gcc.target/arm/pr44788.c	(revision 0)
+++ testsuite/gcc.target/arm/pr44788.c	(revision 0)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
+
+void joint_decode(float* mlt_buffer1, int t) {
+    int i;
+    float decode_buffer[1060];
+    foo(decode_buffer);
+    for (i=0; i<10 ; i++) {
+        mlt_buffer1[i] = i * decode_buffer[t];
+    }
+}
Index: config/arm/thumb2.md
===================================================================
--- config/arm/thumb2.md	(revision 161725)
+++ config/arm/thumb2.md	(working copy)
@@ -467,7 +467,7 @@ (define_insn "*thumb2_arith_shiftsi"
           [(match_operator:SI 3 "shift_operator"
              [(match_operand:SI 4 "s_register_operand" "r")
               (match_operand:SI 5 "const_int_operand" "M")])
-           (match_operand:SI 2 "s_register_operand" "r")]))]
+           (match_operand:SI 2 "s_register_operand" "rk")]))]
   "TARGET_THUMB2"
   "%i1%?\\t%0, %2, %4%S3"
   [(set_attr "predicable" "yes")
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 161726)
+++ config/arm/arm.md	(working copy)
@@ -9006,7 +9006,7 @@ (define_insn "*arith_shiftsi"
           [(match_operator:SI 3 "shift_operator"
              [(match_operand:SI 4 "s_register_operand" "r")
               (match_operand:SI 5 "reg_or_int_operand" "rI")])
-           (match_operand:SI 2 "s_register_operand" "r")]))]
+           (match_operand:SI 2 "s_register_operand" "rk")]))]
   "TARGET_ARM"
   "%i1%?\\t%0, %2, %4%S3"
   [(set_attr "predicable" "yes")