From patchwork Sat Jul 3 11:23:43 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 57802 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C1190B6ED0 for ; Sat, 3 Jul 2010 21:24:43 +1000 (EST) Received: (qmail 28419 invoked by alias); 3 Jul 2010 11:24:41 -0000 Received: (qmail 28405 invoked by uid 22791); 3 Jul 2010 11:24:39 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, TW_QE, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 03 Jul 2010 11:24:33 +0000 Received: (qmail 22190 invoked from network); 3 Jul 2010 11:24:31 -0000 Received: from unknown (HELO ?84.152.219.37?) (bernds@127.0.0.2) by mail.codesourcery.com with ESMTPA; 3 Jul 2010 11:24:31 -0000 Message-ID: <4C2F1DBF.8060500@codesourcery.com> Date: Sat, 03 Jul 2010 13:23:43 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100625 Thunderbird/3.0.5 MIME-Version: 1.0 To: GCC Patches Subject: ARM patch: Fix PR44787/44788 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This fixes an ICE which is caused by reload generating an invalid instruction. While reloading a complex addressing mode, it generates (insn 98 55 59 2 pr44788.c:6 (set (reg:SI 5 r5) (plus:SI (mult:SI (reg/v:SI 5 r5 [orig:183 t ] [183]) (const_int 4 [0x4])) (reg/f:SI 13 sp))) 661 {*thumb2_arith_shiftsi} (nil)) There isn't actually anything wrong with this, except the pattern doesn't allow the stack pointer - but the machine does. Hence, the following patch. I've added the testcase in two places; the copy in gcc.target uses the compilation flags in the PR (which are necessary to reproduce the bug). Regression tested on: Target is arm-none-linux-gnueabi Host is i686-pc-linux-gnu Schedule of variations: qemu-system-armv7/arch=armv7-a/thumb qemu-system-armv7/thumb qemu-system-armv7 Ok? Bernd PR rtl-optimization/44787 * config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2. * config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise. PR rtl-optimization/44787 * gcc.c-torture/compile/pr44788.c: New test. * gcc.target/arm/pr44788.c: New test. Index: testsuite/gcc.c-torture/compile/pr44788.c =================================================================== --- testsuite/gcc.c-torture/compile/pr44788.c (revision 0) +++ testsuite/gcc.c-torture/compile/pr44788.c (revision 0) @@ -0,0 +1,8 @@ +void joint_decode(float* mlt_buffer1, int t) { + int i; + float decode_buffer[1060]; + foo(decode_buffer); + for (i=0; i<10 ; i++) { + mlt_buffer1[i] = i * decode_buffer[t]; + } +} Index: testsuite/gcc.target/arm/pr44788.c =================================================================== --- testsuite/gcc.target/arm/pr44788.c (revision 0) +++ testsuite/gcc.target/arm/pr44788.c (revision 0) @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ + +void joint_decode(float* mlt_buffer1, int t) { + int i; + float decode_buffer[1060]; + foo(decode_buffer); + for (i=0; i<10 ; i++) { + mlt_buffer1[i] = i * decode_buffer[t]; + } +} Index: config/arm/thumb2.md =================================================================== --- config/arm/thumb2.md (revision 161725) +++ config/arm/thumb2.md (working copy) @@ -467,7 +467,7 @@ (define_insn "*thumb2_arith_shiftsi" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "const_int_operand" "M")]) - (match_operand:SI 2 "s_register_operand" "r")]))] + (match_operand:SI 2 "s_register_operand" "rk")]))] "TARGET_THUMB2" "%i1%?\\t%0, %2, %4%S3" [(set_attr "predicable" "yes") Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 161726) +++ config/arm/arm.md (working copy) @@ -9006,7 +9006,7 @@ (define_insn "*arith_shiftsi" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "reg_or_int_operand" "rI")]) - (match_operand:SI 2 "s_register_operand" "r")]))] + (match_operand:SI 2 "s_register_operand" "rk")]))] "TARGET_ARM" "%i1%?\\t%0, %2, %4%S3" [(set_attr "predicable" "yes")