diff mbox

Use non-zero address for CRC calculations

Message ID 1454459458-7177-1-git-send-email-swarren@wwwdotorg.org
State Accepted, archived
Headers show

Commit Message

Stephen Warren Feb. 3, 2016, 12:30 a.m. UTC 
From: Stephen Warren <swarren@nvidia.com>

Currently, U-Boot's itest command cannot read from address 0. On Tegra20,
soc['ram-base'] can be 0, and is the address passed to itest. Modify the
code to use an offset from this address, so as not to use address 0.

Note that in Tegra30 and later, the RAM base is non-zero, so this issue
does not occur. This issue also only affects the "flash" command, and not
the "exec" command.

A patch is also in progress to fix the itest command in U-Boot. However,
fixing tegra-uboot-flasher not to use address 0 seems reasonable too, and
will immediately solve the issue irrespective of which U-Boot code-base is
in use.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Untested so far since I'm working from home today due to snowfall and can't
remotely plug in my old Tegra20 HW. I'll test before I apply this tomorrow.

 tegra-uboot-flasher | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

Comments

Stephen Warren Feb. 3, 2016, 4:43 p.m. UTC | #1 
On 02/02/2016 05:30 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Currently, U-Boot's itest command cannot read from address 0. On Tegra20,
> soc['ram-base'] can be 0, and is the address passed to itest. Modify the
> code to use an offset from this address, so as not to use address 0.
>
> Note that in Tegra30 and later, the RAM base is non-zero, so this issue
> does not occur. This issue also only affects the "flash" command, and not
> the "exec" command.
>
> A patch is also in progress to fix the itest command in U-Boot. However,
> fixing tegra-uboot-flasher not to use address 0 seems reasonable too, and
> will immediately solve the issue irrespective of which U-Boot code-base is
> in use.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> Untested so far since I'm working from home today due to snowfall and can't
> remotely plug in my old Tegra20 HW. I'll test before I apply this tomorrow.

Tested on Seaboard/Springbank and Jetson TK1, and applied.
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diff mbox

Patch

diff --git a/tegra-uboot-flasher b/tegra-uboot-flasher
index 0fefe21dc211..153db0dafb8e 100755
--- a/tegra-uboot-flasher
+++ b/tegra-uboot-flasher
@@ -206,14 +206,15 @@  def func_flash():
         cmd = ['fdtput', '-p', '-t', 'x', u_boot_dtb_runflash, '/config', 'bootdelay', '0xfffffffe']
         run(workdir, cmd)
 
+        crc_addr = soc['ram-base'] + 4
         bootcmd = ''
         bootcmd += 'echo >>> Verifying image in RAM... ; '
-        bootcmd += 'crc32 0x%08x 0x%08x 0x%08x ; ' % (flash_image_addr, flash_img_size, soc['ram-base'])
-        bootcmd += 'if itest.l *0x%08x != 0x%x; then echo CRC MISMATCH of initial image; exit; fi ; ' % (soc['ram-base'], flash_img_crc32_bs)
+        bootcmd += 'crc32 0x%08x 0x%08x 0x%08x ; ' % (flash_image_addr, flash_img_size, crc_addr)
+        bootcmd += 'if itest.l *0x%08x != 0x%x; then echo CRC MISMATCH of initial image; exit; fi ; ' % (crc_addr, flash_img_crc32_bs)
         bootcmd += gen_flashcmd(flash_image_addr, readback_addr, flash_img_size)
         bootcmd += 'echo >>> Verifying image from flash... ; '
-        bootcmd += 'crc32 0x%08x 0x%08x 0x%08x ; ' % (readback_addr, flash_img_size, soc['ram-base'])
-        bootcmd += 'if itest.l *0x%08x != 0x%x; then echo CRC MISMATCH of readback image; exit; fi ; ' % (soc['ram-base'], flash_img_crc32_bs)
+        bootcmd += 'crc32 0x%08x 0x%08x 0x%08x ; ' % (readback_addr, flash_img_size, crc_addr)
+        bootcmd += 'if itest.l *0x%08x != 0x%x; then echo CRC MISMATCH of readback image; exit; fi ; ' % (crc_addr, flash_img_crc32_bs)
         bootcmd += 'echo >>> Setting up environment... ; '
         bootcmd += 'env default -f -a ; '
         # Perhaps U-Boot should set $boardname based on the ID EEPROM; then we wouldn't need this