[v2,2/3] clocksource: Add NPS400 timers driver
diff mbox

Message ID 1454418899-25500-3-git-send-email-noamc@ezchip.com
State Superseded
Headers show

Commit Message

Noam Camus Feb. 2, 2016, 1:14 p.m. UTC
From: Noam Camus <noamc@ezchip.com>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
---
 .../bindings/timer/ezchip,nps400-timer.txt         |   15 ++++
 drivers/clocksource/Kconfig                        |    7 ++
 drivers/clocksource/Makefile                       |    1 +
 drivers/clocksource/timer-nps.c                    |   84 ++++++++++++++++++++
 4 files changed, 107 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

Comments

kbuild test robot Feb. 2, 2016, 2:36 p.m. UTC | #1
Hi Noam,

[auto build test WARNING on tip/irq/core]
[also build test WARNING on v4.5-rc2 next-20160201]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160202-213530
config: x86_64-allmodconfig (attached as .config)
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   In file included from drivers/clocksource/timer-nps.c:24:0:
   include/soc/nps/common.h: In function 'nps_host_reg_non_cl':
>> include/soc/nps/common.h:122:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
     return (void *)reg_address.value;
            ^
   include/soc/nps/common.h: In function 'nps_host_reg':
   include/soc/nps/common.h:136:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
     return (void *)reg_address.value;
            ^

vim +122 include/soc/nps/common.h

f44c724c Noam Camus 2016-02-02  106  	union {
f44c724c Noam Camus 2016-02-02  107  		struct {
f44c724c Noam Camus 2016-02-02  108  			u32 base:7, blkid:11, reg:12, __reserved:2;
f44c724c Noam Camus 2016-02-02  109  		};
f44c724c Noam Camus 2016-02-02  110  		u32 value;
f44c724c Noam Camus 2016-02-02  111  	};
f44c724c Noam Camus 2016-02-02  112  };
f44c724c Noam Camus 2016-02-02  113  
f44c724c Noam Camus 2016-02-02  114  static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02  115  {
f44c724c Noam Camus 2016-02-02  116  	struct nps_host_reg_address_non_cl reg_address;
f44c724c Noam Camus 2016-02-02  117  
f44c724c Noam Camus 2016-02-02  118  	reg_address.value = NPS_HOST_REG_BASE;
f44c724c Noam Camus 2016-02-02  119  	reg_address.blkid = blkid;
f44c724c Noam Camus 2016-02-02  120  	reg_address.reg = reg;
f44c724c Noam Camus 2016-02-02  121  
f44c724c Noam Camus 2016-02-02 @122  	return (void *)reg_address.value;
f44c724c Noam Camus 2016-02-02  123  }
f44c724c Noam Camus 2016-02-02  124  
f44c724c Noam Camus 2016-02-02  125  static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
f44c724c Noam Camus 2016-02-02  126  {
f44c724c Noam Camus 2016-02-02  127  	struct nps_host_reg_address reg_address;
f44c724c Noam Camus 2016-02-02  128  	u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
f44c724c Noam Camus 2016-02-02  129  
f44c724c Noam Camus 2016-02-02  130  	reg_address.value = NPS_HOST_REG_BASE;

:::::: The code at line 122 was first introduced by commit
:::::: f44c724ca34c57edebb15cae51eaa8d9b6976526 soc: Support for EZchip SoC

:::::: TO: Noam Camus <noamc@ezchip.com>
:::::: CC: 0day robot <fengguang.wu@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@ 
+NPS Network Processor
+
+Required properties:
+
+- compatible :	should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+	compatible = "ezchip,nps400-timer";
+	clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..859e83d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,13 @@  config CLKSRC_TI_32K
 	  This option enables support for Texas Instruments 32.768 Hz clocksource
 	  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+	bool "NPS400 clocksource driver" if COMPILE_TEST
+	select CLKSRC_OF if OF
+	help
+	  NPS400 clocksource support.
+	  Got 64 bit counter with update rate up to 1000MHz.
+
 config CLKSRC_STM32
 	bool "Clocksource for STM32 SoCs" if !ARCH_STM32
 	depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@  obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO)	+= time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)	+= timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@ 
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW	0xC8
+#define NPS_CLUSTER_OFFSET	8
+#define NPS_CLUSTER_NUM		16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+	int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+	return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+	.name	= "EZnps-tick",
+	.rating = 301,
+	.read   = nps_clksrc_read,
+	.mask   = CLOCKSOURCE_MASK(32),
+	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+					 struct clk *clk)
+{
+	struct clocksource *clksrc = &nps_counter;
+	int ret, cluster;
+
+	for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+		nps_msu_reg_low_addr[cluster] =
+			nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+				 NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+	ret = clk_prepare_enable(clk);
+	if (ret)
+		pr_err("Couldn't enable parent clock\n");
+
+	nps_timer_rate = clk_get_rate(clk);
+
+	ret = clocksource_register_hz(clksrc, nps_timer_rate);
+	if (ret)
+		pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+	struct clk *clk;
+
+	clk = of_clk_get(node, 0);
+	if (IS_ERR(clk))
+		panic("Can't get timer clock");
+
+	nps_setup_clocksource(node, clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+		       nps_timer_init);