From patchwork Thu Jul 1 13:19:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Zhang X-Patchwork-Id: 57549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 47A22100824 for ; Thu, 1 Jul 2010 23:20:05 +1000 (EST) Received: (qmail 6881 invoked by alias); 1 Jul 2010 13:20:03 -0000 Received: (qmail 6809 invoked by uid 22791); 1 Jul 2010 13:20:02 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 01 Jul 2010 13:19:54 +0000 Received: (qmail 20978 invoked from network); 1 Jul 2010 13:19:52 -0000 Received: from unknown (HELO ?192.168.0.124?) (jie@127.0.0.2) by mail.codesourcery.com with ESMTPA; 1 Jul 2010 13:19:52 -0000 Message-ID: <4C2C95F5.9000000@codesourcery.com> Date: Thu, 01 Jul 2010 21:19:49 +0800 From: Jie Zhang User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.4) Gecko/20100608 Lightning/1.0b2 Thunderbird/3.1 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: Richard Henderson Subject: [ARM] Remove register constraints from push multiple patterns (was Re: [PATCH] Provide a hook for target to disable register renaming for some instructions) References: <4C2B84B7.2000506@codesourcery.com> <4C2B86EF.6020900@redhat.com> In-Reply-To: <4C2B86EF.6020900@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 07/01/2010 02:03 AM, Richard Henderson wrote: > On 06/30/2010 10:53 AM, Jie Zhang wrote: >> When compiler an application for ARM, the GAS issued a warning: >> >> Warning: register range not in ascending order >> >> for the instruction >> >> push {ip, r3, r4, lr} >> >> Before regrename pass, this instruction looked like >> >> push {r0, r3, r4, lr} > > Doesn't it work just as well to simply remove the register > constraint from the push_multi instruction? Without that > the regrename pass won't get a register class for the > operand and will leave it alone. > According to Richard's comment, a new patch is attached. It removes register constraints from all three push multiple patterns. Since there are no constraints for operand 1 of *push_multi_vfp, I use a new predicate to make it more stricter. Tested on arm-none-eabi for NEON and non-NEON. No regressions found. Is it OK? Regards, * config/arm/vfp.md (*push_multi_vfp): Use vfp_register_operand as predicate for operand 1 and remove its constraint. * config/arm/predicates.md (vfp_register_operand): New. * config/arm/arm.md (*push_multi): Remove the constraint of operand 1. (*push_fp_multi): Likewise. Index: config/arm/vfp.md =================================================================== --- config/arm/vfp.md (revision 161654) +++ config/arm/vfp.md (working copy) @@ -1132,7 +1132,7 @@ (define_insn "*push_multi_vfp" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")] + (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* return vfp_output_fstmd (operands);" Index: config/arm/predicates.md =================================================================== --- config/arm/predicates.md (revision 161654) +++ config/arm/predicates.md (working copy) @@ -73,6 +73,21 @@ || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); }) +(define_predicate "vfp_register_operand" + (match_code "reg,subreg") +{ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + /* We don't consider registers whose class is NO_REGS + to be a register operand. */ + return (GET_CODE (op) == REG + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS + || (TARGET_VFPD32 + && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); +}) + (define_special_predicate "subreg_lowpart_operator" (and (match_code "subreg") (match_test "subreg_lowpart_p (op)"))) Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 161654) +++ config/arm/arm.md (working copy) @@ -10871,7 +10871,7 @@ (define_insn "*push_multi" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] + (unspec:BLK [(match_operand:SI 1 "s_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT" "* @@ -10924,7 +10924,7 @@ (define_insn "*push_fp_multi" [(match_parallel 2 "multi_register_push" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:XF 1 "f_register_operand" "f")] + (unspec:BLK [(match_operand:XF 1 "f_register_operand" "")] UNSPEC_PUSH_MULT))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "*