| Message ID | 1453460848-21808-5-git-send-email-aneesh.bansal@nxp.com |
|---|---|
| State | Accepted |
| Delegated to: | York Sun |
| Headers | show |
> -----Original Message----- > From: Aneesh Bansal [mailto:aneesh.bansal@nxp.com] > Sent: Friday, January 22, 2016 4:37 PM > To: u-boot@lists.denx.de > Cc: york sun <york.sun@nxp.com>; Ruchika Gupta > <ruchika.gupta@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Aneesh Bansal > <aneesh.bansal@nxp.com> > Subject: [PATCH v3 4/7] create function to determine boot mode > > A function is created to detrmine if the boot mode is secure or non-secure > for differnt SoC's. > > Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> > --- > Changes in v3: > None > > Changes in v2: > Corrected the macro for SB_EN bit in RCW. > > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++ > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + > arch/powerpc/include/asm/immap_85xx.h | 3 ++ > board/freescale/common/fsl_chain_of_trust.c | 53 > ++++++++++++++++++++++ > 4 files changed, 61 insertions(+) > create mode 100644 board/freescale/common/fsl_chain_of_trust.c > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > index 21b803f..297ff35 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h > @@ -218,6 +218,9 @@ struct ccsr_gur { > #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f > #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 > #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 > +#define RCW_SB_EN_REG_INDEX 7 > +#define RCW_SB_EN_MASK 0x00200000 > + > u8 res_140[0x200-0x140]; > u32 scratchrw[4]; /* Scratch Read/Write */ > u8 res_210[0x300-0x210]; > diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > index 89339fe..0a80772 100644 > --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > @@ -120,6 +120,8 @@ struct ccsr_gur { > u32 brrl; /* Boot release */ > u8 res_0e8[0x100-0xe8]; > u32 rcwsr[16]; /* Reset control word status */ > +#define RCW_SB_EN_REG_INDEX 7 > +#define RCW_SB_EN_MASK 0x00200000 > u8 res_140[0x200-0x140]; > u32 scratchrw[4]; /* Scratch Read/Write */ > u8 res_210[0x300-0x210]; > diff --git a/arch/powerpc/include/asm/immap_85xx.h > b/arch/powerpc/include/asm/immap_85xx.h > index bc7e5f8..53ca6d9 100644 > --- a/arch/powerpc/include/asm/immap_85xx.h > +++ b/arch/powerpc/include/asm/immap_85xx.h > @@ -1749,6 +1749,8 @@ typedef struct ccsr_gur { > u32 brrl; /* Boot release */ > u8 res17[24]; > u32 rcwsr[16]; /* Reset control word status */ > +#define RCW_SB_EN_REG_INDEX 7 > +#define RCW_SB_EN_MASK 0x00200000 > > #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 > #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 > @@ -2193,6 +2195,7 @@ typedef struct ccsr_gur { > #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 > #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 > #endif > +#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 > /* The 8544 RM says this is bit 26, but it's really bit 24 */ > #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 > u8 res1[8]; > diff --git a/board/freescale/common/fsl_chain_of_trust.c > b/board/freescale/common/fsl_chain_of_trust.c > new file mode 100644 > index 0000000..ff67bd7 > --- /dev/null > +++ b/board/freescale/common/fsl_chain_of_trust.c > @@ -0,0 +1,53 @@ > +/* > + * Copyright 2015 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <fsl_validate.h> > +#include <fsl_sfp.h> > + > +#ifdef CONFIG_LS102XA > +#include <asm/arch/immap_ls102xa.h> > +#endif > + > +#if defined(CONFIG_MPC85xx) > +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR > +#else > +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR > +#endif > + > +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE > +#define gur_in32(a) in_le32(a) > +#else > +#define gur_in32(a) in_be32(a) > +#endif > + > +/* Check the Boot Mode. If Secure, return 1 else return 0 */ int > +fsl_check_boot_mode_secure(void) { > + uint32_t val; > + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); > + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); > + > + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; > + if (val == ITS_MASK) > + return 1; > + > +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) > + /* For PBL based platforms check the SB_EN bit in RCWSR */ > + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & > RCW_SB_EN_MASK; > + if (val == RCW_SB_EN_MASK) > + return 1; > +#endif > + > +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) > + /* For Non-PBL Platforms, check the Device Status register 2*/ > + val = gur_in32(&gur->pordevsr2) & > MPC85xx_PORDEVSR2_SBC_MASK; > + if (val != MPC85xx_PORDEVSR2_SBC_MASK) > + return 1; > + > +#endif > + return 0; > +} > -- > 1.8.1.4 Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
On 01/22/2016 03:10 AM, Aneesh Bansal wrote: > A function is created to detrmine if the boot mode is secure > or non-secure for differnt SoC's. > > Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> > --- > Changes in v3: > None > > Changes in v2: > Corrected the macro for SB_EN bit in RCW. > > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++ > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + > arch/powerpc/include/asm/immap_85xx.h | 3 ++ > board/freescale/common/fsl_chain_of_trust.c | 53 ++++++++++++++++++++++ > 4 files changed, 61 insertions(+) > create mode 100644 board/freescale/common/fsl_chain_of_trust.c Prefix subject with "secure_boot:". Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks. York
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 21b803f..297ff35 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -218,6 +218,9 @@ struct ccsr_gur { #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 89339fe..0a80772 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -120,6 +120,8 @@ struct ccsr_gur { u32 brrl; /* Boot release */ u8 res_0e8[0x100-0xe8]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index bc7e5f8..53ca6d9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1749,6 +1749,8 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 @@ -2193,6 +2195,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif +#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c new file mode 100644 index 0000000..ff67bd7 --- /dev/null +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_validate.h> +#include <fsl_sfp.h> + +#ifdef CONFIG_LS102XA +#include <asm/arch/immap_ls102xa.h> +#endif + +#if defined(CONFIG_MPC85xx) +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#else +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +}
A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> --- Changes in v3: None Changes in v2: Corrected the macro for SB_EN bit in RCW. .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/powerpc/include/asm/immap_85xx.h | 3 ++ board/freescale/common/fsl_chain_of_trust.c | 53 ++++++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 board/freescale/common/fsl_chain_of_trust.c