| Message ID | 1453072320-24298-51-git-send-email-sjg@chromium.org |
|---|---|
| State | Accepted |
| Commit | 278d3a4444cd89214be7951d7493716990361b7b |
| Delegated to: | Bin Meng |
| Headers | show |
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass <sjg@chromium.org> wrote: > This is not needed. On reset wake-on-disconnect is already set. It may a > problem during a soft reset or resume, but for now it does not seem > important. Also drop the command register update since PCI auto-config > does it for us. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v2: > - Rename from 'Convert EHCI init to use the DM PCI API' > - Drop this init > - Fix the USB PCI address in the device tree > > arch/x86/cpu/ivybridge/Makefile | 1 - > arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- > arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- > arch/x86/dts/chromebook_link.dts | 12 +++++++++++ > arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - > 5 files changed, 12 insertions(+), 34 deletions(-) > delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Thu, Jan 21, 2016 at 3:39 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass <sjg@chromium.org> wrote: >> This is not needed. On reset wake-on-disconnect is already set. It may a >> problem during a soft reset or resume, but for now it does not seem >> important. Also drop the command register update since PCI auto-config >> does it for us. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> Changes in v2: >> - Rename from 'Convert EHCI init to use the DM PCI API' >> - Drop this init >> - Fix the USB PCI address in the device tree >> >> arch/x86/cpu/ivybridge/Makefile | 1 - >> arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- >> arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- >> arch/x86/dts/chromebook_link.dts | 12 +++++++++++ >> arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - >> 5 files changed, 12 insertions(+), 34 deletions(-) >> delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c >> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> applied to u-boot-x86/master, thanks!
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 7007d5f..ac41853 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,5 +17,4 @@ obj-y += northbridge.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o -obj-y += usb_ehci.o obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 70a0aea..2591b20 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -159,9 +159,6 @@ static int bd82x6x_probe(struct udevice *dev) /* Cause the SATA device to do its init */ uclass_first_device(UCLASS_DISK, &dev); - bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); - bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); - gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); if (gma_node < 0) { debug("%s: Cannot find GMA node\n", __func__); diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c deleted file mode 100644 index da11aee..0000000 --- a/arch/x86/cpu/ivybridge/usb_ehci.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -void bd82x6x_usb_ehci_init(pci_dev_t dev) -{ - u32 reg32; - - /* Disable Wake on Disconnect in RMH */ - reg32 = readl(RCB_REG(0x35b0)); - reg32 |= 0x22; - writel(reg32, RCB_REG(0x35b0)); - - debug("EHCI: Setting up controller.. "); - reg32 = x86_pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - /* reg32 |= PCI_COMMAND_SERR; */ - x86_pci_write_config32(dev, PCI_COMMAND, reg32); - - debug("done.\n"); -} diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 329eae8..662e5d9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -12,6 +12,8 @@ aliases { spi0 = "/pci/pch/spi"; + usb0 = &usb_0; + usb1 = &usb_1; }; config { @@ -226,6 +228,16 @@ u-boot,dm-pre-reloc; }; + usb_1: usb@1a,0 { + reg = <0x0000d000 0 0 0 0>; + compatible = "ehci-pci"; + }; + + usb_0: usb@1d,0 { + reg = <0x0000e800 0 0 0 0>; + compatible = "ehci-pci"; + }; + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x", "intel,pch9"; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index bb3a6c9..5959717 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,7 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H -void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node);
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Rename from 'Convert EHCI init to use the DM PCI API' - Drop this init - Fix the USB PCI address in the device tree arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- arch/x86/dts/chromebook_link.dts | 12 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 12 insertions(+), 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c