diff mbox

[U-Boot,v2,17/55] x86: ivybridge: Move GPIO init to the LPC init() method

Message ID 1453072320-24298-18-git-send-email-sjg@chromium.org
State Accepted
Delegated to: Bin Meng
Headers show

Commit Message

Simon Glass Jan. 17, 2016, 11:11 p.m. UTC
This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/cpu/ivybridge/cpu.c | 4 ----
 arch/x86/cpu/ivybridge/lpc.c | 3 +++
 2 files changed, 3 insertions(+), 4 deletions(-)

Comments

Bin Meng Jan. 21, 2016, 8 a.m. UTC | #1
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass <sjg@chromium.org> wrote:
> This init can happen in the driver also. Move it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/ivybridge/cpu.c | 4 ----
>  arch/x86/cpu/ivybridge/lpc.c | 3 +++
>  2 files changed, 3 insertions(+), 4 deletions(-)
>

applied to u-boot-x86/master, thanks!
diff mbox

Patch

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c3626c4..6d3f477 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -278,10 +278,6 @@  int print_cpuinfo(void)
 
 	gd->arch.pei_boot_mode = boot_mode;
 
-	/* TODO: Move this to the board or driver */
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index c88733d..0d85de2 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -623,6 +623,9 @@  static int bd82x6x_lpc_early_init(struct udevice *dev)
 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */
 	outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
 
+	dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+	dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
 	return 0;
 }