diff mbox

[U-Boot,3/4] tegra: video: Always use write-through cache on LCD

Message ID 1452803219-16675-4-git-send-email-sjg@chromium.org
State Accepted
Commit 8d37483e7cfff9e36a928379d7ab6c4fc11bd4c1
Delegated to: Tom Warren
Headers show

Commit Message

Simon Glass Jan. 14, 2016, 8:26 p.m. UTC
This seems to give the best performance, so let's use it always.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/video/tegra.c | 21 +++------------------
 1 file changed, 3 insertions(+), 18 deletions(-)

Comments

Stephen Warren Jan. 18, 2016, 8:07 p.m. UTC | #1
On 01/14/2016 01:26 PM, Simon Glass wrote:
> This seems to give the best performance, so let's use it always.

I thought we chose the current cache mode due to display corruption 
issues with other modes, but I tested a change that I believe does the 
same as this change on Seaboard without any apparent issue so,

Acked-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding Jan. 20, 2016, 2:53 p.m. UTC | #2
On Mon, Jan 18, 2016 at 01:07:10PM -0700, Stephen Warren wrote:
> On 01/14/2016 01:26 PM, Simon Glass wrote:
> >This seems to give the best performance, so let's use it always.
> 
> I thought we chose the current cache mode due to display corruption issues
> with other modes, but I tested a change that I believe does the same as this
> change on Seaboard without any apparent issue so,
> 
> Acked-by: Stephen Warren <swarren@nvidia.com>

I think for framebuffers the best option is still write-combine, which
would be something like:

	DCACHE_WRITECOMBINE = DCACHE_OFF | TTB_SECT_B_MASK

on ARM v7. Did you ever benchmark that against DCACHE_WRITETHROUGH? It
should be faster provided that you never read from the region.

Thierry
Simon Glass Jan. 20, 2016, 4:18 p.m. UTC | #3
Hi Thierry,

On 20 January 2016 at 07:53, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Jan 18, 2016 at 01:07:10PM -0700, Stephen Warren wrote:
>> On 01/14/2016 01:26 PM, Simon Glass wrote:
>> >This seems to give the best performance, so let's use it always.
>>
>> I thought we chose the current cache mode due to display corruption issues
>> with other modes, but I tested a change that I believe does the same as this
>> change on Seaboard without any apparent issue so,
>>
>> Acked-by: Stephen Warren <swarren@nvidia.com>
>
> I think for framebuffers the best option is still write-combine, which
> would be something like:
>
>         DCACHE_WRITECOMBINE = DCACHE_OFF | TTB_SECT_B_MASK
>
> on ARM v7. Did you ever benchmark that against DCACHE_WRITETHROUGH? It
> should be faster provided that you never read from the region.

This is noticeably slower in my experience. Reading from the region is
pretty common - e.g. scrolling.

Regards,
Simon
diff mbox

Patch

diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index d34189d..cb2a157 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -22,15 +22,6 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-enum lcd_cache_t {
-	FDT_LCD_CACHE_OFF		= 0,
-	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
-	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
-	FDT_LCD_CACHE_FLUSH		= 1 << 2,
-	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
-						FDT_LCD_CACHE_FLUSH,
-};
-
 /* Information about the display controller */
 struct tegra_lcd_priv {
 	int width;			/* width in pixels */
@@ -41,7 +32,6 @@  struct tegra_lcd_priv {
 	struct disp_ctlr *disp;		/* Display controller to use */
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	enum lcd_cache_t cache_type;
 };
 
 enum {
@@ -310,7 +300,6 @@  static int tegra_lcd_probe(struct udevice *dev)
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
-	int type = DCACHE_OFF;
 	int ret;
 
 	/* Initialize the Tegra display controller */
@@ -330,15 +319,11 @@  static int tegra_lcd_probe(struct udevice *dev)
 		return ret;
 	}
 
-	/* Set up the LCD caching as requested */
-	if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
-		type = DCACHE_WRITETHROUGH;
-	else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
-		type = DCACHE_WRITEBACK;
-	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
+	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
+					DCACHE_WRITETHROUGH);
 
 	/* Enable flushing after LCD writes if requested */
-	video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
+	video_set_flush_dcache(dev, true);
 
 	uc_priv->xsize = priv->width;
 	uc_priv->ysize = priv->height;