From patchwork Wed Jun 23 20:49:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxim Kuvyrkov X-Patchwork-Id: 56718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 79948B6EE8 for ; Thu, 24 Jun 2010 06:49:45 +1000 (EST) Received: (qmail 8496 invoked by alias); 23 Jun 2010 20:49:41 -0000 Received: (qmail 8476 invoked by uid 22791); 23 Jun 2010 20:49:38 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 23 Jun 2010 20:49:29 +0000 Received: (qmail 27846 invoked from network); 23 Jun 2010 20:49:27 -0000 Received: from unknown (HELO ?172.16.1.24?) (maxim@127.0.0.2) by mail.codesourcery.com with ESMTPA; 23 Jun 2010 20:49:27 -0000 Message-ID: <4C227355.60505@codesourcery.com> Date: Thu, 24 Jun 2010 00:49:25 +0400 From: Maxim Kuvyrkov User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; en-US; rv:1.9.1.10) Gecko/20100512 Thunderbird/3.0.5 MIME-Version: 1.0 To: Richard Earnshaw CC: gcc-patches Subject: Re: ARM improvements for GCSE References: <4C18F225.2040509@codesourcery.com> <4C227243.9080104@codesourcery.com> In-Reply-To: <4C227243.9080104@codesourcery.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch improves handling of "J" and "K" constants. If a pseudo assigned a constant and set only once, IRA/reload can rematerialize it to decrease high register pressure. OK to check in? diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5057bac..5671587 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6931,6 +6931,10 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) return 0; + /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ + if (INTVAL (x) >= -255 && INTVAL (x) <= -1) + return COSTS_N_INSNS (2); + /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ if (thumb_shiftable_const (INTVAL (x))) return COSTS_N_INSNS (2); return COSTS_N_INSNS (3); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 628bd62..b6cca49 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5191,17 +5191,21 @@ [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" - [(set (match_dup 0) (match_dup 1)) - (set (match_dup 0) (neg:SI (match_dup 0)))] - "operands[1] = GEN_INT (- INTVAL (operands[1]));" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (neg:SI (match_dup 2)))] + " + { + operands[1] = GEN_INT (- INTVAL (operands[1])); + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; + }" ) (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" - [(set (match_dup 0) (match_dup 1)) - (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))] " { unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu; @@ -5212,12 +5216,13 @@ if ((val & (mask << i)) == val) break; - /* Shouldn't happen, but we don't want to split if the shift is zero. */ + /* Don't split if the shift is zero. */ if (i == 0) FAIL; operands[1] = GEN_INT (val >> i); - operands[2] = GEN_INT (i); + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; + operands[3] = GEN_INT (i); }" )