@@ -196,6 +196,7 @@ static void sdhci_reset(SDHCIState *s)
sd_set_cb(s->card, s->ro_cb, s->eject_cb);
s->data_count = 0;
s->stopped_state = sdhc_not_stopped;
+ s->pending_insert = false;
}
static void sdhci_data_transfer(void *opaque);
@@ -1087,6 +1088,12 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
} else {
s->norintsts &= ~SDHC_NIS_ERR;
}
+ /* Quirk for Raspberry Pi: pending card insert interrupt
+ * appears when first enabled after power on */
+ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert) {
+ s->norintsts |= SDHC_NIS_INSERT;
+ s->pending_insert = false;
+ }
sdhci_update_irq(s);
break;
case SDHC_NORINTSIGEN:
@@ -1180,7 +1187,7 @@ static void sdhci_uninitfn(SDHCIState *s)
const VMStateDescription sdhci_vmstate = {
.name = "sdhci",
- .version_id = 1,
+ .version_id = 2,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(sdmasysad, SDHCIState),
@@ -1211,6 +1218,7 @@ const VMStateDescription sdhci_vmstate = {
VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz),
VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
+ VMSTATE_BOOL(pending_insert, SDHCIState),
VMSTATE_END_OF_LIST()
}
};
@@ -1227,6 +1235,8 @@ static Property sdhci_pci_properties[] = {
DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
SDHC_CAPAB_REG_DEFAULT),
DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
+ DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert,
+ false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -77,6 +77,7 @@ typedef struct SDHCIState {
uint32_t buf_maxsz;
uint16_t data_count; /* current element in FIFO buffer */
uint8_t stopped_state;/* Current SDHC state */
+ bool pending_insert;/* Quirk for Raspberry Pi card insert interrupt */
/* Buffer Data Port Register - virtual access point to R and W buffers */
/* Software Reset Register - always reads as 0 */
/* Force Event Auto CMD12 Error Interrupt Reg - write only */
This quirk is a workaround for the following hardware behaviour, on which UEFI (specifically, the bootloader for Windows on Pi2) depends: 1. at boot with an SD card present, the interrupt status/enable registers are initially zero 2. upon enabling it in the interrupt enable register, the card insert bit in the interrupt status register is immediately set 3. after a subsequent controller reset, the card insert interrupt does not fire, even if enabled in the interrupt enable register The implementation uses a pending_insert bool, which can be set via a property (enabling the quirk) and is cleared and remains clear once the interrupt has been delivered. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> --- This depends on https://lists.gnu.org/archive/html/qemu-devel/2015-12/msg04895.html (revert of the broken noeject_quirk). Notes: v2: changed implementation to use pending_insert bool rather than masking norintsts at read time, since the older version diverges from actual hardware behaviour when an interrupt is masked without being acked Peter, am I doing the right thing with the vmstate here? hw/sd/sdhci.c | 12 +++++++++++- include/hw/sd/sdhci.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-)