| Message ID | 1452330464-16386-3-git-send-email-sr@denx.de |
|---|---|
| State | Accepted |
| Commit | a5f88877af9ae7d9f462efcbc5cb6fd7be9af106 |
| Delegated to: | Stefan Roese |
| Headers | show |
On 01/09/2016 03:07 AM, Stefan Roese wrote: > @@ -100,14 +100,24 @@ > #if defined(CONFIG_ARMADA_38X) > /* SAR values for Armada 38x */ > #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) > + > #define SAR_CPU_FREQ_OFFS 10 > #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) > #define SAR_BOOT_DEVICE_OFFS 4 > #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) > + > +#define BOOT_DEV_SEL_OFFS 4 > +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS) > + It is a little confusing that this is added incorrectly here, then corrected in the next patch ... could this just be added as 0x3f here? > +#define BOOT_FROM_UART 0x28 > +#define BOOT_FROM_SPI 0x32 > +#define BOOT_FROM_MMC 0x30 > +#define BOOT_FROM_MMC_ALT 0x31 >
On 13.01.2016 17:12, Kevin Smith wrote: > On 01/09/2016 03:07 AM, Stefan Roese wrote: >> @@ -100,14 +100,24 @@ >> #if defined(CONFIG_ARMADA_38X) >> /* SAR values for Armada 38x */ >> #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) >> + >> #define SAR_CPU_FREQ_OFFS 10 >> #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) >> #define SAR_BOOT_DEVICE_OFFS 4 >> #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) >> + >> +#define BOOT_DEV_SEL_OFFS 4 >> +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS) >> + > It is a little confusing that this is added incorrectly here, then > corrected in the next patch ... could this just be added as 0x3f here? Ah, right. I've fixed this define in the next patch: arm: mvebu: Add runtime detection of UART (xmodem) boot-mode Which is already waiting for upstreaming as well (once Luka picks it up). I hope this is okay. Otherwise I would need to re-do those patches again. Thanks, Stefan
On 01/13/2016 10:18 AM, Stefan Roese wrote: > On 13.01.2016 17:12, Kevin Smith wrote: >> On 01/09/2016 03:07 AM, Stefan Roese wrote: >>> @@ -100,14 +100,24 @@ >>> #if defined(CONFIG_ARMADA_38X) >>> /* SAR values for Armada 38x */ >>> #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) >>> + >>> #define SAR_CPU_FREQ_OFFS 10 >>> #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) >>> #define SAR_BOOT_DEVICE_OFFS 4 >>> #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) >>> + >>> +#define BOOT_DEV_SEL_OFFS 4 >>> +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS) >>> + >> It is a little confusing that this is added incorrectly here, then >> corrected in the next patch ... could this just be added as 0x3f here? > > Ah, right. I've fixed this define in the next patch: > > arm: mvebu: Add runtime detection of UART (xmodem) boot-mode > > Which is already waiting for upstreaming as well (once Luka picks it > up). I hope this is okay. Otherwise I would need to re-do those > patches again. > > Thanks, > Stefan > Oh, sure, no problem. Not worth redoing that work. Thanks, Kevin
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index dbb96e0..0da313d 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -100,14 +100,24 @@ #if defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) + #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) #define SAR_BOOT_DEVICE_OFFS 4 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 4 +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SPI 0x32 +#define BOOT_FROM_MMC 0x30 +#define BOOT_FROM_MMC_ALT 0x31 #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) + #define SAR_CPU_FREQ_OFFS 21 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) #define SAR_FFC_FREQ_OFFS 24 @@ -116,6 +126,12 @@ #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) #define SAR_BOOT_DEVICE_OFFS 5 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 5 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 #endif #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 832df0a..778996e 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,14 +15,30 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) +static u32 get_boot_device(void) { -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) - return BOOT_DEVICE_SPI; -#endif -#if defined(CONFIG_SPL_MMC_SUPPORT) - return BOOT_DEVICE_MMC1; + u32 val; + u32 boot_device; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + switch (boot_device) { +#ifdef CONFIG_SPL_MMC_SUPPORT + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; #endif + case BOOT_FROM_UART: + return BOOT_DEVICE_UART; + case BOOT_FROM_SPI: + default: + return BOOT_DEVICE_SPI; + }; +} + +u32 spl_boot_device(void) +{ + return get_boot_device(); } #ifdef CONFIG_SPL_MMC_SUPPORT
This patch adds runtime boot-device detection to SPL U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> --- arch/arm/mach-mvebu/include/mach/soc.h | 16 ++++++++++++++++ arch/arm/mach-mvebu/spl.c | 30 +++++++++++++++++++++++------- 2 files changed, 39 insertions(+), 7 deletions(-)