@@ -1631,6 +1631,64 @@ static void build_piix4_pci0_int(Aml *table)
aml_append(table, sb_scope);
}
+static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
+{
+ int i;
+ int head;
+ Aml *pkg;
+ char base = name[3] < 'E' ? 'A' : 'E';
+ char *s = g_strdup(name);
+ Aml *a_nr = aml_int((nr << 16) | 0xffff);
+
+ assert(strlen(s) == 4);
+
+ head = name[3] - base;
+ for (i = 0; i < 4; i++) {
+ if (head + i > 3) {
+ head = i * -1;
+ }
+ s[3] = base + head + i;
+ pkg = aml_package(4);
+ aml_append(pkg, a_nr);
+ aml_append(pkg, aml_int(i));
+ aml_append(pkg, aml_name("%s", s));
+ aml_append(pkg, aml_int(0));
+ aml_append(ctx, pkg);
+ }
+ g_free(s);
+}
+
+static Aml *build_q35_routing_table(const char *str)
+{
+ int i;
+ Aml *pkg;
+ char *name = g_strdup_printf("%s ", str);
+
+ pkg = aml_package(128);
+ for (i = 0; i < 0x18; i++) {
+ name[3] = 'E' + (i & 0x3);
+ append_q35_prt_entry(pkg, i, name);
+ }
+
+ name[3] = 'E';
+ append_q35_prt_entry(pkg, 0x18, name);
+
+ /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
+ for (i = 0x0019; i < 0x1e; i++) {
+ name[3] = 'A';
+ append_q35_prt_entry(pkg, i, name);
+ }
+
+ /* PCIe->PCI bridge. use PIRQ[E-H] */
+ name[3] = 'E';
+ append_q35_prt_entry(pkg, 0x1e, name);
+ name[3] = 'A';
+ append_q35_prt_entry(pkg, 0x1f, name);
+
+ g_free(name);
+ return pkg;
+}
+
static void build_q35_pci0_int(Aml *table)
{
Aml *field;
@@ -1638,6 +1696,9 @@ static void build_q35_pci0_int(Aml *table)
Aml *sb_scope = aml_scope("_SB");
Aml *pci0_scope = aml_scope("PCI0");
+ aml_append(pci0_scope,
+ aml_name_decl("PRTA", build_q35_routing_table("GSI")));
+
method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
{
Aml *if_ctx;
@@ -181,63 +181,6 @@ DefinitionBlock (
prt_slot_lnkA(0x001f)
})
-
-#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
- Package() { nr##ffff, 0, gsi0, 0 }, \
- Package() { nr##ffff, 1, gsi1, 0 }, \
- Package() { nr##ffff, 2, gsi2, 0 }, \
- Package() { nr##ffff, 3, gsi3, 0 }
-
-#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
-#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
-#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
-#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
-
-#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
-#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
-#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
-#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
-
- Name(PRTA, package() {
- prt_slot_gsiE(0x0000),
- prt_slot_gsiF(0x0001),
- prt_slot_gsiG(0x0002),
- prt_slot_gsiH(0x0003),
- prt_slot_gsiE(0x0004),
- prt_slot_gsiF(0x0005),
- prt_slot_gsiG(0x0006),
- prt_slot_gsiH(0x0007),
- prt_slot_gsiE(0x0008),
- prt_slot_gsiF(0x0009),
- prt_slot_gsiG(0x000a),
- prt_slot_gsiH(0x000b),
- prt_slot_gsiE(0x000c),
- prt_slot_gsiF(0x000d),
- prt_slot_gsiG(0x000e),
- prt_slot_gsiH(0x000f),
- prt_slot_gsiE(0x0010),
- prt_slot_gsiF(0x0011),
- prt_slot_gsiG(0x0012),
- prt_slot_gsiH(0x0013),
- prt_slot_gsiE(0x0014),
- prt_slot_gsiF(0x0015),
- prt_slot_gsiG(0x0016),
- prt_slot_gsiH(0x0017),
- prt_slot_gsiE(0x0018),
-
- /* INTA -> PIRQA for slot 25 - 31, but 30
- see the default value of D<N>IR */
- prt_slot_gsiA(0x0019),
- prt_slot_gsiA(0x001a),
- prt_slot_gsiA(0x001b),
- prt_slot_gsiA(0x001c),
- prt_slot_gsiA(0x001d),
-
- /* PCIe->PCI bridge. use PIRQ[E-H] */
- prt_slot_gsiE(0x001e),
-
- prt_slot_gsiA(0x001f)
- })
}
External(LNKA, DeviceObj)