Message ID | 20151231204119.GA8942@ibm-tiger.the-meissners.org |
---|---|
State | New |
Headers | show |
On Thu, Dec 31, 2015 at 3:41 PM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > When I did the inital d-form support for ISA 3.0 (power9) for loading scalar > SF/DF values into Altivec registers, I did not enable -mpower9-dform with the > other ISA 3.0 switches when you used -mcpu=power9. This was during the initial > development, I had some bugs. I fixed the bugs, but I forgot to enable the > d-form addressing support. This patch enables that default. > > I have built all of Spec 2006 with this option, and there were no failures. I > did not do the full bootstrap/make check right now, but I have done it in the > past with no regressions. Is it ok to install this patch? > > 2015-12-31 Michael Meissner <meissner@linux.vnet.ibm.com> > > * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add > OPTION_MASK_P9_DFORM. > > (Note, at some point there will be patches to enable using d-form addressing > with 128-bit vector types, but those patches aren't ready yet). This is okay. Thanks, David
Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 232017) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -67,6 +67,7 @@ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ + | OPTION_MASK_P9_DFORM \ | OPTION_MASK_P9_VECTOR) #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)