diff mbox

[U-Boot,2/2] arm: Remove S bit from MMU section entry

Message ID 1451414642-21289-2-git-send-email-marex@denx.de
State Accepted
Commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Delegated to: Albert ARIBAUD
Headers show

Commit Message

Marek Vasut Dec. 29, 2015, 6:44 p.m. UTC 
Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
---
 arch/arm/include/asm/system.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index dec83c7..8d64d23 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -235,8 +235,7 @@  static inline void set_dacr(unsigned int val)
 
 /* options available for data cache on each page */
 enum dcache_option {
-	DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
-					TTB_SECT_XN_MASK | TTB_SECT,
+	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
 	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
 	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
 	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),