[v5,04/20] clocksource: Add NPS400 timers driver
diff mbox

Message ID 1451222619-3610-5-git-send-email-noamc@ezchip.com
State Deferred
Headers show

Commit Message

Noam Camus Dec. 27, 2015, 1:23 p.m. UTC
From: Noam Camus <noamc@ezchip.com>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
---
 .../bindings/timer/ezchip,nps400-timer.txt         |   17 ++
 drivers/clocksource/Kconfig                        |    7 +
 drivers/clocksource/Makefile                       |    1 +
 drivers/clocksource/timer-nps.c                    |  199 ++++++++++++++++++++
 4 files changed, 224 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

Comments

kbuild test robot Dec. 27, 2015, 2:55 p.m. UTC | #1
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
Hi Noam,

[auto build test ERROR on arc/for-next]
[also build test ERROR on v4.4-rc6 next-20151223]

url:    https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-plat-eznps-to-ARC/20151227-220433
base:   https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
config: i386-allmodconfig (attached as .config)
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/clocksource/timer-nps.c: In function 'nps_timer_event_setup':
>> drivers/clocksource/timer-nps.c:60:2: error: implicit declaration of function 'write_aux_reg' [-Werror=implicit-function-declaration]
     write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
     ^
   drivers/clocksource/timer-nps.c: In function 'nps_timer_cpu_notify':
>> drivers/clocksource/timer-nps.c:106:3: error: implicit declaration of function 'enable_percpu_irq' [-Werror=implicit-function-declaration]
      enable_percpu_irq(nps_timer_irq, 0);
      ^
>> drivers/clocksource/timer-nps.c:111:3: error: implicit declaration of function 'disable_percpu_irq' [-Werror=implicit-function-declaration]
      disable_percpu_irq(nps_timer_irq);
      ^
   drivers/clocksource/timer-nps.c: In function 'nps_setup_clocksource':
   drivers/clocksource/timer-nps.c:148:6: error: 'NPS_MSU_BLKID' undeclared (first use in this function)
         NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
         ^
   drivers/clocksource/timer-nps.c:148:6: note: each undeclared identifier is reported only once for each function it appears in
   drivers/clocksource/timer-nps.c: In function 'nps_setup_clockevents':
>> drivers/clocksource/timer-nps.c:176:8: error: implicit declaration of function 'request_percpu_irq' [-Werror=implicit-function-declaration]
     ret = request_percpu_irq(irq, nps_timer_irq_handler,
           ^
   cc1: some warnings being treated as errors

vim +/write_aux_reg +60 drivers/clocksource/timer-nps.c

    54		.mask   = CLOCKSOURCE_MASK(32),
    55		.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
    56	};
    57	
    58	static void nps_timer_event_setup(unsigned int cycles)
    59	{
  > 60		write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
    61		write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
    62	
    63		write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
    64	}
    65	
    66	static int nps_clkevent_set_next_event(unsigned long delta,
    67					       struct clock_event_device *dev)
    68	{
    69		nps_timer_event_setup(delta);
    70		return 0;
    71	}
    72	
    73	static int nps_clkevent_set_periodic(struct clock_event_device *dev)
    74	{
    75		/*
    76		 * At X Hz, 1 sec = 1000ms -> X cycles;
    77		 *                    10ms -> X / 100 cycles
    78		 */
    79		nps_timer_event_setup(nps_timer_rate / HZ);
    80		return 0;
    81	}
    82	
    83	static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
    84		.name			= "nps_sys_timer",
    85		.features               = CLOCK_EVT_FEAT_ONESHOT |
    86					  CLOCK_EVT_FEAT_PERIODIC,
    87		.rating                 = 300,
    88		.set_next_event         = nps_clkevent_set_next_event,
    89		.set_state_periodic     = nps_clkevent_set_periodic,
    90	};
    91	
    92	static int nps_timer_cpu_notify(struct notifier_block *self,
    93					unsigned long action, void *hcpu)
    94	{
    95		struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
    96	
    97		evt->irq = nps_timer_irq;
    98		evt->cpumask = cpumask_of(smp_processor_id());
    99	
   100		/*
   101		 * Grab cpu pointer in each case to avoid spurious
   102		 * preemptible warnings
   103		 */
   104		switch (action & ~CPU_TASKS_FROZEN) {
   105		case CPU_STARTING:
 > 106			enable_percpu_irq(nps_timer_irq, 0);
   107			clockevents_config_and_register(evt, nps_timer_rate,
   108							0, ULONG_MAX);
   109			break;
   110		case CPU_DYING:
 > 111			disable_percpu_irq(nps_timer_irq);
   112			break;
   113		}
   114	
   115		return NOTIFY_OK;
   116	}
   117	
   118	static struct notifier_block nps_timer_cpu_nb = {
   119		.notifier_call = nps_timer_cpu_notify,
   120	};
   121	
   122	static irqreturn_t nps_timer_irq_handler(int irq, void *dev_id)
   123	{
   124		struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
   125		int irq_reenable = clockevent_state_periodic(evt);
   126	
   127		/*
   128		 * Any write to CTRL reg ACks the interrupt, we rewrite the
   129		 * Count when [N]ot [H]alted bit.
   130		 * And re-arm it if perioid by [I]nterrupt [E]nable bit
   131		 */
   132		write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
   133	
   134		evt->event_handler(evt);
   135	
   136		return IRQ_HANDLED;
   137	}
   138	
   139	static void __init nps_setup_clocksource(struct device_node *node,
   140						 struct clk *clk, int irq)
   141	{
   142		struct clocksource *clksrc = &nps_counter;
   143		int ret, cluster;
   144	
   145		for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
   146			nps_msu_reg_low_addr[cluster] =
   147				nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
   148					 NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
   149	
   150		ret = clk_prepare_enable(clk);
   151		if (ret)
   152			pr_err("Couldn't enable parent clock\n");
   153	
   154		nps_timer_rate = clk_get_rate(clk);
   155	
   156		ret = clocksource_register_hz(clksrc, nps_timer_rate);
   157		if (ret)
   158			pr_err("Couldn't register clock source.\n");
   159	}
   160	
   161	static void __init nps_setup_clockevents(struct device_node *node,
   162						 struct clk *clk, int irq)
   163	{
   164		struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
   165		int ret;
   166	
   167		register_cpu_notifier(&nps_timer_cpu_nb);
   168	
   169		evt->irq = irq;
   170		evt->cpumask = cpumask_of(smp_processor_id());
   171	
   172		clockevents_config_and_register(evt, nps_timer_rate, 0, ULONG_MAX);
   173	
   174		enable_percpu_irq(irq, 0);
   175	
 > 176		ret = request_percpu_irq(irq, nps_timer_irq_handler,
   177					 "timer", evt);
   178		if (ret)
   179			pr_err("Unable to register interrupt\n");

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Daniel Lezcano Dec. 28, 2015, 9 a.m. UTC | #2
On 12/27/2015 10:41 PM, Noam Camus wrote:
>> From: kbuild test robot <lkp@intel.com>
>> Sent: Sunday, December 27, 2015 4:55 PM
>
>> [if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
>> Hi Noam,
>
>> [auto build test ERROR on arc/for-next]
>> [also build test ERROR on v4.4-rc6 next-20151223]
>
>> url:    https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-plat-eznps-to-ARC/20151227-220433
>> base:   https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
>> config: i386-allmodconfig (attached as .config)
>> reproduce:
>>        # save the attached .config to linux build tree
>>       make ARCH=i386
>
> This is meant for ARC only (not i386), I will add to the Kconfig file a dependency on my platform.

Hi Noam,

for compilation test coverage it would be nice to not restrict the to 
ARC only but change the write_aux_reg to a common name across the 
different arch if possible.

   -- Daniel
Vineet Gupta Dec. 28, 2015, 10:35 a.m. UTC | #3
On Monday 28 December 2015 02:30 PM, Daniel Lezcano wrote:
>>> reproduce:
>>>        # save the attached .config to linux build tree
>>>       make ARCH=i386
>>
>> This is meant for ARC only (not i386), I will add to the Kconfig file a
>> dependency on my platform.
> 
> Hi Noam,
> 
> for compilation test coverage it would be nice to not restrict the to ARC only but
> change the write_aux_reg to a common name across the different arch if possible.
> 
>   -- Daniel

Hi Daniel,

AUX registers is a ARC specific mechanism used to access some of the core
functionality (intc, caches, ....) which other arches likely do via MMIO. I don't
think a generic abstraction exists. And IMHO it doesn't make sense to invent one
given this may not map directly to other arches.

This was one of the key reasons arc intc/timers were not added to drivers/* in
first place.

I do agree with compilation test coverage aspect though.
Maybe we add a *hack* to include/soc/nps/common.h

#ifndef __ARC__
#define  write_aux_reg(r, v)
#define  read_aux_reg(r) 0
#endif

What say you ?

-Vineet
Daniel Lezcano Dec. 28, 2015, 10:55 a.m. UTC | #4
On 12/28/2015 11:35 AM, Vineet Gupta wrote:
> On Monday 28 December 2015 02:30 PM, Daniel Lezcano wrote:
>>>> reproduce:
>>>>         # save the attached .config to linux build tree
>>>>        make ARCH=i386
>>>
>>> This is meant for ARC only (not i386), I will add to the Kconfig file a
>>> dependency on my platform.
>>
>> Hi Noam,
>>
>> for compilation test coverage it would be nice to not restrict the to ARC only but
>> change the write_aux_reg to a common name across the different arch if possible.
>>
>>    -- Daniel
>
> Hi Daniel,
>
> AUX registers is a ARC specific mechanism used to access some of the core
> functionality (intc, caches, ....) which other arches likely do via MMIO. I don't
> think a generic abstraction exists. And IMHO it doesn't make sense to invent one
> given this may not map directly to other arches.
>
> This was one of the key reasons arc intc/timers were not added to drivers/* in
> first place.
>
> I do agree with compilation test coverage aspect though.
> Maybe we add a *hack* to include/soc/nps/common.h
>
> #ifndef __ARC__
> #define  write_aux_reg(r, v)
> #define  read_aux_reg(r) 0
> #endif
>
> What say you ?

Yes that's an alternative.

Perhaps instead of the __ARC__:

/*
  * Define dummy macros to let different architectures to
  * compile test some drivers, eg. the timer.
  */
#ifndef write_aux_reg
#define write_aux_reg(r, v)
#endif

#ifndef read_aux_reg
#define read_aux_reg(r) 0
#endif

Now that header must be included always *after* asm/arcregs.h.

Not sure this kind of implicit ordering is not prone to bug.
Vineet Gupta Dec. 28, 2015, 11:11 a.m. UTC | #5
On Monday 28 December 2015 04:25 PM, Daniel Lezcano wrote:
> On 12/28/2015 11:35 AM, Vineet Gupta wrote:
>> On Monday 28 December 2015 02:30 PM, Daniel Lezcano wrote:
>>>>> reproduce:
>>>>>         # save the attached .config to linux build tree
>>>>>        make ARCH=i386
>>>>
>>>> This is meant for ARC only (not i386), I will add to the Kconfig file a
>>>> dependency on my platform.
>>>
>>> Hi Noam,
>>>
>>> for compilation test coverage it would be nice to not restrict the to ARC only but
>>> change the write_aux_reg to a common name across the different arch if possible.
>>>
>>>    -- Daniel
>>
>> Hi Daniel,
>>
>> AUX registers is a ARC specific mechanism used to access some of the core
>> functionality (intc, caches, ....) which other arches likely do via MMIO. I don't
>> think a generic abstraction exists. And IMHO it doesn't make sense to invent one
>> given this may not map directly to other arches.
>>
>> This was one of the key reasons arc intc/timers were not added to drivers/* in
>> first place.
>>
>> I do agree with compilation test coverage aspect though.
>> Maybe we add a *hack* to include/soc/nps/common.h
>>
>> #ifndef __ARC__
>> #define  write_aux_reg(r, v)
>> #define  read_aux_reg(r) 0
>> #endif
>>
>> What say you ?
> 
> Yes that's an alternative.
> 
> Perhaps instead of the __ARC__:
> 
> /*
>  * Define dummy macros to let different architectures to
>  * compile test some drivers, eg. the timer.
>  */
> #ifndef write_aux_reg
> #define write_aux_reg(r, v)
> #endif
> 
> #ifndef read_aux_reg
> #define read_aux_reg(r) 0
> #endif
> 
> Now that header must be included always *after* asm/arcregs.h.
> 
> Not sure this kind of implicit ordering is not prone to bug.

Indeed, this all seems too fragile. The main point here is to allow building of
this code on !ARC and that can simply be done with my original proposal, w/o
adding any other ordering rules/dependencies for ARC builds !

-Vineet
Vineet Gupta Jan. 1, 2016, 10:31 a.m. UTC | #6
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
> 
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
> 
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>

Not quite.

Also it would help if your individual patches record which changed vs. prev
version (vs. doing that just in cover letter).

So this patch is no longer clocksource as you introduce clockevent as well.
And that is a verbose copy/paste of clockevent in arch/arc/kerne/time.c
I do understand why you did this - since ARC timers have not been DT enabled so
far. But the copy/paste is simply *wrong*.

I'm doing a mini-series which fixes the issue at heart.

It will be a series with incremental changes so we clearly see what is being done.

> ---
>  .../bindings/timer/ezchip,nps400-timer.txt         |   17 ++
>  drivers/clocksource/Kconfig                        |    7 +
>  drivers/clocksource/Makefile                       |    1 +
>  drivers/clocksource/timer-nps.c                    |  199 ++++++++++++++++++++
>  4 files changed, 224 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
>  create mode 100644 drivers/clocksource/timer-nps.c
> 
> diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> new file mode 100644
> index 0000000..eeb26d7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> @@ -0,0 +1,17 @@
> +NPS Network Processor
> +
> +Required properties:
> +
> +- compatible :	should be "ezchip,nps400-timer"
> +
> +Clocks required for compatible = "ezchip,nps400-timer":
> +- clocks : Must contain a single entry describing the clock input
> +- interrupts : The interrupt of the first timer
> +
> +Example:
> +
> +timer {
> +	compatible = "ezchip,nps400-timer";
> +	clocks = <&sysclk>;
> +	interrupts = <3>;
> +};
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 2eb5f0e..859e83d 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -132,6 +132,13 @@ config CLKSRC_TI_32K
>  	  This option enables support for Texas Instruments 32.768 Hz clocksource
>  	  available on many OMAP-like platforms.
>  
> +config CLKSRC_NPS
> +	bool "NPS400 clocksource driver" if COMPILE_TEST
> +	select CLKSRC_OF if OF
> +	help
> +	  NPS400 clocksource support.
> +	  Got 64 bit counter with update rate up to 1000MHz.
> +
>  config CLKSRC_STM32
>  	bool "Clocksource for STM32 SoCs" if !ARCH_STM32
>  	depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 56bd16e..056cffd 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
>  obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
>  obj-$(CONFIG_CLKSRC_PISTACHIO)	+= time-pistachio.o
>  obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o
> +obj-$(CONFIG_CLKSRC_NPS)	+= timer-nps.o
>  
>  obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
>  obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o
> diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
> new file mode 100644
> index 0000000..b3fc9ba
> --- /dev/null
> +++ b/drivers/clocksource/timer-nps.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright(c) 2015 EZchip Technologies.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * The full GNU General Public License is included in this distribution in
> + * the file called "COPYING".
> + */
> +
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/cpu.h>
> +#include <soc/nps/common.h>
> +
> +#define NPS_MSU_TICK_LOW	0xC8
> +#define NPS_CLUSTER_OFFSET	8
> +#define NPS_CLUSTER_NUM		16
> +
> +/* Timer related Aux registers */
> +#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
> +#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
> +#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
> +
> +#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
> +#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
> +
> +/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
> +static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
> +
> +static unsigned long nps_timer_rate;
> +static int nps_timer_irq;
> +
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> +	int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
> +
> +	return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
> +}
> +
> +static struct clocksource nps_counter = {
> +	.name	= "EZnps-tick",
> +	.rating = 301,
> +	.read   = nps_clksrc_read,
> +	.mask   = CLOCKSOURCE_MASK(32),
> +	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void nps_timer_event_setup(unsigned int cycles)
> +{
> +	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
> +	write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
> +
> +	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
> +}
> +
> +static int nps_clkevent_set_next_event(unsigned long delta,
> +				       struct clock_event_device *dev)
> +{
> +	nps_timer_event_setup(delta);
> +	return 0;
> +}
> +
> +static int nps_clkevent_set_periodic(struct clock_event_device *dev)
> +{
> +	/*
> +	 * At X Hz, 1 sec = 1000ms -> X cycles;
> +	 *                    10ms -> X / 100 cycles
> +	 */
> +	nps_timer_event_setup(nps_timer_rate / HZ);
> +	return 0;
> +}
> +
> +static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
> +	.name			= "nps_sys_timer",
> +	.features               = CLOCK_EVT_FEAT_ONESHOT |
> +				  CLOCK_EVT_FEAT_PERIODIC,
> +	.rating                 = 300,
> +	.set_next_event         = nps_clkevent_set_next_event,
> +	.set_state_periodic     = nps_clkevent_set_periodic,
> +};
> +
> +static int nps_timer_cpu_notify(struct notifier_block *self,
> +				unsigned long action, void *hcpu)
> +{
> +	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> +
> +	evt->irq = nps_timer_irq;
> +	evt->cpumask = cpumask_of(smp_processor_id());
> +
> +	/*
> +	 * Grab cpu pointer in each case to avoid spurious
> +	 * preemptible warnings
> +	 */
> +	switch (action & ~CPU_TASKS_FROZEN) {
> +	case CPU_STARTING:
> +		enable_percpu_irq(nps_timer_irq, 0);
> +		clockevents_config_and_register(evt, nps_timer_rate,
> +						0, ULONG_MAX);
> +		break;
> +	case CPU_DYING:
> +		disable_percpu_irq(nps_timer_irq);
> +		break;
> +	}
> +
> +	return NOTIFY_OK;
> +}
> +
> +static struct notifier_block nps_timer_cpu_nb = {
> +	.notifier_call = nps_timer_cpu_notify,
> +};
> +
> +static irqreturn_t nps_timer_irq_handler(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> +	int irq_reenable = clockevent_state_periodic(evt);
> +
> +	/*
> +	 * Any write to CTRL reg ACks the interrupt, we rewrite the
> +	 * Count when [N]ot [H]alted bit.
> +	 * And re-arm it if perioid by [I]nterrupt [E]nable bit
> +	 */
> +	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static void __init nps_setup_clocksource(struct device_node *node,
> +					 struct clk *clk, int irq)
> +{
> +	struct clocksource *clksrc = &nps_counter;
> +	int ret, cluster;
> +
> +	for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
> +		nps_msu_reg_low_addr[cluster] =
> +			nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
> +				 NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
> +
> +	ret = clk_prepare_enable(clk);
> +	if (ret)
> +		pr_err("Couldn't enable parent clock\n");
> +
> +	nps_timer_rate = clk_get_rate(clk);
> +
> +	ret = clocksource_register_hz(clksrc, nps_timer_rate);
> +	if (ret)
> +		pr_err("Couldn't register clock source.\n");
> +}
> +
> +static void __init nps_setup_clockevents(struct device_node *node,
> +					 struct clk *clk, int irq)
> +{
> +	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> +	int ret;
> +
> +	register_cpu_notifier(&nps_timer_cpu_nb);
> +
> +	evt->irq = irq;
> +	evt->cpumask = cpumask_of(smp_processor_id());
> +
> +	clockevents_config_and_register(evt, nps_timer_rate, 0, ULONG_MAX);
> +
> +	enable_percpu_irq(irq, 0);
> +
> +	ret = request_percpu_irq(irq, nps_timer_irq_handler,
> +				 "timer", evt);
> +	if (ret)
> +		pr_err("Unable to register interrupt\n");
> +}
> +
> +static void __init nps_timer_init(struct device_node *node)
> +{
> +	struct clk *clk;
> +
> +	nps_timer_irq = irq_of_parse_and_map(node, 0);
> +	if (nps_timer_irq <= 0)
> +		panic("Can't parse IRQ");
> +
> +	clk = of_clk_get(node, 0);
> +	if (IS_ERR(clk))
> +		panic("Can't get timer clock");
> +
> +	nps_setup_clocksource(node, clk, nps_timer_irq);
> +	nps_setup_clockevents(node, clk, nps_timer_irq);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
> +		       nps_timer_init);
>

Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 0000000..eeb26d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,17 @@ 
+NPS Network Processor
+
+Required properties:
+
+- compatible :	should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+- interrupts : The interrupt of the first timer
+
+Example:
+
+timer {
+	compatible = "ezchip,nps400-timer";
+	clocks = <&sysclk>;
+	interrupts = <3>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..859e83d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,13 @@  config CLKSRC_TI_32K
 	  This option enables support for Texas Instruments 32.768 Hz clocksource
 	  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+	bool "NPS400 clocksource driver" if COMPILE_TEST
+	select CLKSRC_OF if OF
+	help
+	  NPS400 clocksource support.
+	  Got 64 bit counter with update rate up to 1000MHz.
+
 config CLKSRC_STM32
 	bool "Clocksource for STM32 SoCs" if !ARCH_STM32
 	depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@  obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO)	+= time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)	+= timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 0000000..b3fc9ba
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,199 @@ 
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/cpu.h>
+#include <soc/nps/common.h>
+
+#define NPS_MSU_TICK_LOW	0xC8
+#define NPS_CLUSTER_OFFSET	8
+#define NPS_CLUSTER_NUM		16
+
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
+#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
+
+#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
+#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+static int nps_timer_irq;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+	int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+	return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+	.name	= "EZnps-tick",
+	.rating = 301,
+	.read   = nps_clksrc_read,
+	.mask   = CLOCKSOURCE_MASK(32),
+	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void nps_timer_event_setup(unsigned int cycles)
+{
+	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
+	write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
+
+	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
+}
+
+static int nps_clkevent_set_next_event(unsigned long delta,
+				       struct clock_event_device *dev)
+{
+	nps_timer_event_setup(delta);
+	return 0;
+}
+
+static int nps_clkevent_set_periodic(struct clock_event_device *dev)
+{
+	/*
+	 * At X Hz, 1 sec = 1000ms -> X cycles;
+	 *                    10ms -> X / 100 cycles
+	 */
+	nps_timer_event_setup(nps_timer_rate / HZ);
+	return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
+	.name			= "nps_sys_timer",
+	.features               = CLOCK_EVT_FEAT_ONESHOT |
+				  CLOCK_EVT_FEAT_PERIODIC,
+	.rating                 = 300,
+	.set_next_event         = nps_clkevent_set_next_event,
+	.set_state_periodic     = nps_clkevent_set_periodic,
+};
+
+static int nps_timer_cpu_notify(struct notifier_block *self,
+				unsigned long action, void *hcpu)
+{
+	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+
+	evt->irq = nps_timer_irq;
+	evt->cpumask = cpumask_of(smp_processor_id());
+
+	/*
+	 * Grab cpu pointer in each case to avoid spurious
+	 * preemptible warnings
+	 */
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_STARTING:
+		enable_percpu_irq(nps_timer_irq, 0);
+		clockevents_config_and_register(evt, nps_timer_rate,
+						0, ULONG_MAX);
+		break;
+	case CPU_DYING:
+		disable_percpu_irq(nps_timer_irq);
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block nps_timer_cpu_nb = {
+	.notifier_call = nps_timer_cpu_notify,
+};
+
+static irqreturn_t nps_timer_irq_handler(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+	int irq_reenable = clockevent_state_periodic(evt);
+
+	/*
+	 * Any write to CTRL reg ACks the interrupt, we rewrite the
+	 * Count when [N]ot [H]alted bit.
+	 * And re-arm it if perioid by [I]nterrupt [E]nable bit
+	 */
+	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+					 struct clk *clk, int irq)
+{
+	struct clocksource *clksrc = &nps_counter;
+	int ret, cluster;
+
+	for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+		nps_msu_reg_low_addr[cluster] =
+			nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+				 NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+	ret = clk_prepare_enable(clk);
+	if (ret)
+		pr_err("Couldn't enable parent clock\n");
+
+	nps_timer_rate = clk_get_rate(clk);
+
+	ret = clocksource_register_hz(clksrc, nps_timer_rate);
+	if (ret)
+		pr_err("Couldn't register clock source.\n");
+}
+
+static void __init nps_setup_clockevents(struct device_node *node,
+					 struct clk *clk, int irq)
+{
+	struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+	int ret;
+
+	register_cpu_notifier(&nps_timer_cpu_nb);
+
+	evt->irq = irq;
+	evt->cpumask = cpumask_of(smp_processor_id());
+
+	clockevents_config_and_register(evt, nps_timer_rate, 0, ULONG_MAX);
+
+	enable_percpu_irq(irq, 0);
+
+	ret = request_percpu_irq(irq, nps_timer_irq_handler,
+				 "timer", evt);
+	if (ret)
+		pr_err("Unable to register interrupt\n");
+}
+
+static void __init nps_timer_init(struct device_node *node)
+{
+	struct clk *clk;
+
+	nps_timer_irq = irq_of_parse_and_map(node, 0);
+	if (nps_timer_irq <= 0)
+		panic("Can't parse IRQ");
+
+	clk = of_clk_get(node, 0);
+	if (IS_ERR(clk))
+		panic("Can't get timer clock");
+
+	nps_setup_clocksource(node, clk, nps_timer_irq);
+	nps_setup_clockevents(node, clk, nps_timer_irq);
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
+		       nps_timer_init);