Message ID | AANLkTimbCSM3Kk-Mq3MhRDyhHAaERR-dXhtuplauB3ki@mail.gmail.com |
---|---|
State | New, archived |
Headers | show |
On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang <haojian.zhuang@gmail.com> wrote: > From 643765e6ae0f37902321f31e14b565896217dd3a Mon Sep 17 00:00:00 2001 > From: Lei Wen <leiwen@marvell.com> > Date: Wed, 2 Jun 2010 21:54:33 +0800 > Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure > > After probe, all info already transfer to driver structure. > There is no need to keep the original flash info. > So that we could safely free the flash info in memory, which may grows > larger when more flash is suported. > Some of the changes should be separated from my POV? Like the change to oob_size, and pxa3xx_nand_resume?
On Fri, Jun 18, 2010 at 2:40 PM, Eric Miao <eric.y.miao@gmail.com> wrote: > On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang > <haojian.zhuang@gmail.com> wrote: >> From 643765e6ae0f37902321f31e14b565896217dd3a Mon Sep 17 00:00:00 2001 >> From: Lei Wen <leiwen@marvell.com> >> Date: Wed, 2 Jun 2010 21:54:33 +0800 >> Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure >> >> After probe, all info already transfer to driver structure. >> There is no need to keep the original flash info. >> So that we could safely free the flash info in memory, which may grows >> larger when more flash is suported. >> > > Some of the changes should be separated from my POV? Like the > change to oob_size, and pxa3xx_nand_resume? > This patch is only servered as the prepraration of latter patch seris... So hard to seperate them...
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index f939083..291610a 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -152,7 +152,6 @@ struct pxa3xx_nand_info { struct nand_chip nand_chip; struct platform_device *pdev; - const struct pxa3xx_nand_flash *flash_info; struct clk *clk; void __iomem *mmio_base; @@ -166,6 +165,7 @@ struct pxa3xx_nand_info { int drcmr_cmd; unsigned char *data_buff; + unsigned char *oob_buff; dma_addr_t data_buff_phys; size_t data_buff_size; int data_dma_ch; @@ -184,7 +184,8 @@ struct pxa3xx_nand_info { int use_ecc; /* use HW ECC ? */ int use_dma; /* use DMA ? */ - size_t data_size; /* data size in FIFO */ + unsigned int page_size; /* page size of attached chip */ + unsigned int data_size; /* data size in FIFO */ int retcode; struct completion cmd_complete; @@ -193,6 +194,10 @@ struct pxa3xx_nand_info { uint32_t ndcb1; uint32_t ndcb2; + /* timing calcuted from setting */ + uint32_t ndtr0cs0; + uint32_t ndtr1cs0; + /* calculated from pxa3xx_nand_flash data */ size_t oob_size; size_t read_id_bytes; @@ -293,6 +298,8 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info, NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); + info->ndtr0cs0 = ndtr0; + info->ndtr1cs0 = ndtr1; nand_writel(info, NDTR0CS0, ndtr0); nand_writel(info, NDTR1CS0, ndtr1);