| Message ID | BLU436-SMTP22A3F84957EBBF285280ADFFE70@phx.gbl |
|---|---|
| State | Superseded |
| Headers | show |
On Thursday, December 24, 2015 at 12:22:00 PM, Wills Wang wrote: > This patch enable work for ar933x SOC, tested on ar9331 board. > > Signed-off-by: Wills Wang <wills.wang@live.com> [...] > diff --git a/arch/mips/config.mk b/arch/mips/config.mk > index 3ebc202..fd50909 100644 > --- a/arch/mips/config.mk > +++ b/arch/mips/config.mk > @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 > -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 > -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 > -Wa,-mips64 > cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 > +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc You can just tune it for MIPS32_R2 , it will be compatible with older toolchains too. I don't think there is much benefit in being so explicit and using mips24kc tuning. > PLATFORM_CPPFLAGS += $(cpuflags-y) > > PLATFORM_CPPFLAGS += -D__MIPS__ [...] > diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S > b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 > index 0000000..18c57de > --- /dev/null > +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S > @@ -0,0 +1,268 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <config.h> > +#include <asm/asm.h> > +#include <asm/regdef.h> > +#include <asm/mipsregs.h> > +#include <asm/addrspace.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define DRAM_K0(x) KSEG0ADDR(x) > +#define DRAM_K1(x) KSEG1ADDR(x) > + > + .text > + .set noreorder > + > +LEAF(ddr_tap_init) > + /* Tap settings for the DDR */ > + li t0, 0xffffffff > + li t1, DRAM_K0(0x500000) > + sw t0, 0x0(t1) > + sw t0, 0x4(t1) > + sw t0, 0x8(t1) > + sw t0, 0xc(t1) > + nop > + nop > + > + li t8, DRAM_K1(0x2000) > + li t0, 0x00 > + li t1, 0x100 > +0: > + andi t2, t0, 0x03 > + li t3, 0x00 > + bne t2, t3,1f > + nop > + li t9, 0x00000000 > + sw t9, 0x0(t8) > + b 2f > + nop Please rewrite this into C, I believe it should be pretty easy. [...] > diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S > b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 > index 0000000..72509ca > --- /dev/null > +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S > @@ -0,0 +1,460 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <config.h> > +#include <asm/asm.h> > +#include <asm/regdef.h> > +#include <asm/mipsregs.h> > +#include <asm/addrspace.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define SET_BIT(val, bit) ((val) | (1 << (bit))) > +#define SET_PLL_PD(val) SET_BIT(val, 30) > +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) > +#define PLL_BYPASS(val) SET_BIT(val, 2) > + > +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ > + (((0x3F & divint) << 10) | \ > + ((0x1F & refdiv) << 16) | \ > + ((0x1 & range) << 21) | \ > + ((0x7 & outdiv) << 23) ) > + > +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ > + (((0x3 & (cpudiv - 1)) << 5) | \ > + ((0x3 & (ddrdiv - 1)) << 10) | \ > + ((0x3 & (ahbdiv - 1)) << 15) ) > + > +/* > + * PLL_CPU_CONFIG_VAL > + * > + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) > + * After PLL configuration we need to clear this bit > + * > + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) > + * > + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) > + * => 32 (0x20) VCOOUT = XTAL * DIV_INT > + * bits 16..20 (5bit) REFDIV (Reference clock divider) > + * => 1 (0x1) [Must start at values 1] > + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) > + * => 0 (0x0) [Doesn't impact clock values] > + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) > + * => 1 (0x1) [0 is illegal!] > + * PLLOUT = VCOOUT * (1/2^OUTDIV) > + */ > +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ > +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) > +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ > +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) > + > +/* > + * PLL_CLK_CONTROL_VAL > + * > + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) > + * After PLL configuration we need to clear this bit > + * > + * Values written into CPU Clock Control Register CLOCK_CONTROL > + * > + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. > + * Software must enable the CPU PLL for normal and > + * then set this bit to 0) > + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) > + * CPU_CLK = PLLOUT / CPU_POST_DIV > + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) > + * DDR_CLK = PLLOUT / DDR_POST_DIV > + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) > + * AHB_CLK = PLLOUT / AHB_POST_DIV > + * > + */ > +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) > + > + .text > + .set noreorder > + > +LEAF(lowlevel_init) > + /* These three WLAN_RESET will avoid original issue */ > + li t3, 0x03 > +1: > + li t0, KSEG1ADDR(AR71XX_RESET_BASE) > + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > + ori t1, t1, 0x0800 > + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > + nop > + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > + li t2, 0xfffff7ff > + and t1, t1, t2 > + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > + nop > + addi t3, t3, -1 > + bnez t3, 1b > + nop This should be also easy to rewrite into C , right ? [...] > diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c > new file mode 100644 > index 0000000..1f58877 > --- /dev/null > +++ b/arch/mips/mach-ath79/cpu.c > @@ -0,0 +1,269 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <asm/arch/ath79.h> > +#include <asm/arch/ar71xx_regs.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +enum ath79_soc_type get_soc_type(void) > +{ > + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; > + u32 id, major, minor; > + > + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); > + major = id & REV_ID_MAJOR_MASK; > + > + switch (major) { > + case REV_ID_MAJOR_AR71XX: > + minor = id & AR71XX_REV_ID_MINOR_MASK; > + switch (minor) { > + case AR71XX_REV_ID_MINOR_AR7130: > + soc = ATH79_SOC_AR7130; > + break; I think you can convert this stuff into a table of sorts, so you won't have such a lengthy code: struct { u32 major; u32 minor; enum soc; } table[] { { REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130, ATH79_SOC_AR7130 }, ... } And just iterate over such table. [...] > +int print_cpuinfo(void) > +{ > + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; > + char *chip = "????"; > + u32 id, major, minor; > + u32 rev = 0; > + u32 ver = 1; > + > + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); > + major = id & REV_ID_MAJOR_MASK; > + > + switch (major) { > + case REV_ID_MAJOR_AR71XX: > + minor = id & AR71XX_REV_ID_MINOR_MASK; > + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; > + rev &= AR71XX_REV_ID_REVISION_MASK; > + switch (minor) { > + case AR71XX_REV_ID_MINOR_AR7130: > + soc = ATH79_SOC_AR7130; > + chip = "7130"; > + break; DTTO here, use table lookup [...] > + > + return 0; > +} > diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c > new file mode 100644 > index 0000000..42539dc > --- /dev/null > +++ b/arch/mips/mach-ath79/dram.c > @@ -0,0 +1,27 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/addrspace.h> > +#include <asm/arch/ddr.h> > + > +phys_size_t initdram(int board_type) > +{ > + uint8_t *addr, *p; > + int i; > + > + ddr_tap_init(); > + addr = (uint8_t *)KSEG1; > + *addr = 0x77; > + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { > + p += 0x1000000; > + *p = i; > + if (*addr != 0x77) > + break; > + } What is this and how does it work ? > + return (phys_size_t)(p - addr); > +} [...] > diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c > new file mode 100644 > index 0000000..0ace05d > --- /dev/null > +++ b/arch/mips/mach-ath79/reset.c > @@ -0,0 +1,55 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <asm/arch/ath79.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) > +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) > +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) > +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) Drop these. > +DECLARE_GLOBAL_DATA_PTR; > + > +void _machine_restart(void) > +{ > + enum ath79_soc_type soc; > + u32 val, reg = 0; > + > + soc = get_soc_type(); > + if (soc_is_ar71xx(soc)) > + reg = AR71XX_RESET_REG_RESET_MODULE; > + else if (soc_is_ar724x(soc)) > + reg = AR724X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar913x(soc)) > + reg = AR913X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar933x(soc)) > + reg = AR933X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar934x(soc)) > + reg = AR934X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca953x(soc)) > + reg = QCA953X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca955x(soc)) > + reg = QCA955X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca956x(soc)) > + reg = QCA956X_RESET_REG_RESET_MODULE; > + else > + puts("Reset register not defined for this SOC\n"); > + > + if (reg) { > + val = RST_READ(reg); > + val |= AR71XX_RESET_FULL_CHIP; > + RST_WRITE(reg, val); setbits_le32() please. > + } > + > + while (1) > + /* NOP */; > +}
On 12/24/2015 07:52 PM, Marek Vasut wrote: > On Thursday, December 24, 2015 at 12:22:00 PM, Wills Wang wrote: >> This patch enable work for ar933x SOC, tested on ar9331 board. >> >> Signed-off-by: Wills Wang <wills.wang@live.com> > [...] > >> diff --git a/arch/mips/config.mk b/arch/mips/config.mk >> index 3ebc202..fd50909 100644 >> --- a/arch/mips/config.mk >> +++ b/arch/mips/config.mk >> @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 >> -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 >> -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 >> -Wa,-mips64 >> cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 >> +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc > You can just tune it for MIPS32_R2 , it will be compatible with older toolchains > too. I don't think there is much benefit in being so explicit and using mips24kc > tuning. > >> PLATFORM_CPPFLAGS += $(cpuflags-y) >> >> PLATFORM_CPPFLAGS += -D__MIPS__ > [...] > >> diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S >> b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 >> index 0000000..18c57de >> --- /dev/null >> +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S >> @@ -0,0 +1,268 @@ >> +/* >> + * (C) Copyright 2015 >> + * Wills Wang, <wills.wang@live.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <config.h> >> +#include <asm/asm.h> >> +#include <asm/regdef.h> >> +#include <asm/mipsregs.h> >> +#include <asm/addrspace.h> >> +#include <asm/arch/ar71xx_regs.h> >> + >> +#define DRAM_K0(x) KSEG0ADDR(x) >> +#define DRAM_K1(x) KSEG1ADDR(x) >> + >> + .text >> + .set noreorder >> + >> +LEAF(ddr_tap_init) >> + /* Tap settings for the DDR */ >> + li t0, 0xffffffff >> + li t1, DRAM_K0(0x500000) >> + sw t0, 0x0(t1) >> + sw t0, 0x4(t1) >> + sw t0, 0x8(t1) >> + sw t0, 0xc(t1) >> + nop >> + nop >> + >> + li t8, DRAM_K1(0x2000) >> + li t0, 0x00 >> + li t1, 0x100 >> +0: >> + andi t2, t0, 0x03 >> + li t3, 0x00 >> + bne t2, t3,1f >> + nop >> + li t9, 0x00000000 >> + sw t9, 0x0(t8) >> + b 2f >> + nop > Please rewrite this into C, I believe it should be pretty easy. > > [...] > >> diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S >> b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 >> index 0000000..72509ca >> --- /dev/null >> +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S >> @@ -0,0 +1,460 @@ >> +/* >> + * (C) Copyright 2015 >> + * Wills Wang, <wills.wang@live.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <config.h> >> +#include <asm/asm.h> >> +#include <asm/regdef.h> >> +#include <asm/mipsregs.h> >> +#include <asm/addrspace.h> >> +#include <asm/arch/ar71xx_regs.h> >> + >> +#define SET_BIT(val, bit) ((val) | (1 << (bit))) >> +#define SET_PLL_PD(val) SET_BIT(val, 30) >> +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) >> +#define PLL_BYPASS(val) SET_BIT(val, 2) >> + >> +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ >> + (((0x3F & divint) << 10) | \ >> + ((0x1F & refdiv) << 16) | \ >> + ((0x1 & range) << 21) | \ >> + ((0x7 & outdiv) << 23) ) >> + >> +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ >> + (((0x3 & (cpudiv - 1)) << 5) | \ >> + ((0x3 & (ddrdiv - 1)) << 10) | \ >> + ((0x3 & (ahbdiv - 1)) << 15) ) >> + >> +/* >> + * PLL_CPU_CONFIG_VAL >> + * >> + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) >> + * After PLL configuration we need to clear this bit >> + * >> + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) >> + * >> + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) >> + * => 32 (0x20) VCOOUT = XTAL * DIV_INT >> + * bits 16..20 (5bit) REFDIV (Reference clock divider) >> + * => 1 (0x1) [Must start at values 1] >> + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) >> + * => 0 (0x0) [Doesn't impact clock values] >> + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) >> + * => 1 (0x1) [0 is illegal!] >> + * PLLOUT = VCOOUT * (1/2^OUTDIV) >> + */ >> +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ >> +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) >> +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ >> +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) >> + >> +/* >> + * PLL_CLK_CONTROL_VAL >> + * >> + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) >> + * After PLL configuration we need to clear this bit >> + * >> + * Values written into CPU Clock Control Register CLOCK_CONTROL >> + * >> + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. >> + * Software must enable the CPU PLL for normal and >> + * then set this bit to 0) >> + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) >> + * CPU_CLK = PLLOUT / CPU_POST_DIV >> + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) >> + * DDR_CLK = PLLOUT / DDR_POST_DIV >> + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) >> + * AHB_CLK = PLLOUT / AHB_POST_DIV >> + * >> + */ >> +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) >> + >> + .text >> + .set noreorder >> + >> +LEAF(lowlevel_init) >> + /* These three WLAN_RESET will avoid original issue */ >> + li t3, 0x03 >> +1: >> + li t0, KSEG1ADDR(AR71XX_RESET_BASE) >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >> + ori t1, t1, 0x0800 >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >> + nop >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >> + li t2, 0xfffff7ff >> + and t1, t1, t2 >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >> + nop >> + addi t3, t3, -1 >> + bnez t3, 1b >> + nop > This should be also easy to rewrite into C , right ? C runtime environment is not available. C stack is not ready before DDR has initialized. > > [...] > >> diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c >> new file mode 100644 >> index 0000000..1f58877 >> --- /dev/null >> +++ b/arch/mips/mach-ath79/cpu.c >> @@ -0,0 +1,269 @@ >> +/* >> + * (C) Copyright 2015 >> + * Wills Wang, <wills.wang@live.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <asm/io.h> >> +#include <asm/addrspace.h> >> +#include <asm/types.h> >> +#include <asm/arch/ath79.h> >> +#include <asm/arch/ar71xx_regs.h> >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +enum ath79_soc_type get_soc_type(void) >> +{ >> + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; >> + u32 id, major, minor; >> + >> + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); >> + major = id & REV_ID_MAJOR_MASK; >> + >> + switch (major) { >> + case REV_ID_MAJOR_AR71XX: >> + minor = id & AR71XX_REV_ID_MINOR_MASK; >> + switch (minor) { >> + case AR71XX_REV_ID_MINOR_AR7130: >> + soc = ATH79_SOC_AR7130; >> + break; > I think you can convert this stuff into a table of sorts, so you won't have > such a lengthy code: > > struct { > u32 major; > u32 minor; > enum soc; > } table[] { > { REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130, ATH79_SOC_AR7130 }, > ... > } > > And just iterate over such table. > > [...] > >> +int print_cpuinfo(void) >> +{ >> + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; >> + char *chip = "????"; >> + u32 id, major, minor; >> + u32 rev = 0; >> + u32 ver = 1; >> + >> + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); >> + major = id & REV_ID_MAJOR_MASK; >> + >> + switch (major) { >> + case REV_ID_MAJOR_AR71XX: >> + minor = id & AR71XX_REV_ID_MINOR_MASK; >> + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; >> + rev &= AR71XX_REV_ID_REVISION_MASK; >> + switch (minor) { >> + case AR71XX_REV_ID_MINOR_AR7130: >> + soc = ATH79_SOC_AR7130; >> + chip = "7130"; >> + break; > DTTO here, use table lookup > > [...] > >> + >> + return 0; >> +} >> diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c >> new file mode 100644 >> index 0000000..42539dc >> --- /dev/null >> +++ b/arch/mips/mach-ath79/dram.c >> @@ -0,0 +1,27 @@ >> +/* >> + * (C) Copyright 2015 >> + * Wills Wang, <wills.wang@live.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <asm/addrspace.h> >> +#include <asm/arch/ddr.h> >> + >> +phys_size_t initdram(int board_type) >> +{ >> + uint8_t *addr, *p; >> + int i; >> + >> + ddr_tap_init(); >> + addr = (uint8_t *)KSEG1; >> + *addr = 0x77; >> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { >> + p += 0x1000000; >> + *p = i; >> + if (*addr != 0x77) >> + break; >> + } > What is this and how does it work ? Physical memory was mapped circularly for this chip. > >> + return (phys_size_t)(p - addr); >> +} > [...] > >> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c >> new file mode 100644 >> index 0000000..0ace05d >> --- /dev/null >> +++ b/arch/mips/mach-ath79/reset.c >> @@ -0,0 +1,55 @@ >> +/* >> + * (C) Copyright 2015 >> + * Wills Wang, <wills.wang@live.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <asm/io.h> >> +#include <asm/addrspace.h> >> +#include <asm/types.h> >> +#include <asm/arch/ath79.h> >> +#include <asm/arch/ar71xx_regs.h> >> + >> +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) >> +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) >> +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) >> +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) > Drop these. > >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +void _machine_restart(void) >> +{ >> + enum ath79_soc_type soc; >> + u32 val, reg = 0; >> + >> + soc = get_soc_type(); >> + if (soc_is_ar71xx(soc)) >> + reg = AR71XX_RESET_REG_RESET_MODULE; >> + else if (soc_is_ar724x(soc)) >> + reg = AR724X_RESET_REG_RESET_MODULE; >> + else if (soc_is_ar913x(soc)) >> + reg = AR913X_RESET_REG_RESET_MODULE; >> + else if (soc_is_ar933x(soc)) >> + reg = AR933X_RESET_REG_RESET_MODULE; >> + else if (soc_is_ar934x(soc)) >> + reg = AR934X_RESET_REG_RESET_MODULE; >> + else if (soc_is_qca953x(soc)) >> + reg = QCA953X_RESET_REG_RESET_MODULE; >> + else if (soc_is_qca955x(soc)) >> + reg = QCA955X_RESET_REG_RESET_MODULE; >> + else if (soc_is_qca956x(soc)) >> + reg = QCA956X_RESET_REG_RESET_MODULE; >> + else >> + puts("Reset register not defined for this SOC\n"); >> + >> + if (reg) { >> + val = RST_READ(reg); >> + val |= AR71XX_RESET_FULL_CHIP; >> + RST_WRITE(reg, val); > setbits_le32() please. Macro setbits_le32() is not available for MIPS architecture. Other, I don't think there is better in being so explicit and using little-endian. >> + } >> + >> + while (1) >> + /* NOP */; >> +} >
On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote: [...] > >> +LEAF(lowlevel_init) > >> + /* These three WLAN_RESET will avoid original issue */ > >> + li t3, 0x03 > >> +1: > >> + li t0, KSEG1ADDR(AR71XX_RESET_BASE) > >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >> + ori t1, t1, 0x0800 > >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >> + nop > >> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >> + li t2, 0xfffff7ff > >> + and t1, t1, t2 > >> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >> + nop > >> + addi t3, t3, -1 > >> + bnez t3, 1b > >> + nop > > > > This should be also easy to rewrite into C , right ? > > C runtime environment is not available. > C stack is not ready before DDR has initialized. Just point the stack into a locked cacheline or some onchip RAM and there you have a C runtime. That should be pretty easy :) [...] > >> +phys_size_t initdram(int board_type) > >> +{ > >> + uint8_t *addr, *p; > >> + int i; > >> + > >> + ddr_tap_init(); > >> + addr = (uint8_t *)KSEG1; > >> + *addr = 0x77; > >> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { > >> + p += 0x1000000; > >> + *p = i; > >> + if (*addr != 0x77) > >> + break; > >> + } > > > > What is this and how does it work ? > > Physical memory was mapped circularly for this chip. Can you please expand on that ? I am not as deep in this chip as you are, so please explain it to me in a bit more detail. > >> + return (phys_size_t)(p - addr); > >> +} > > [...] > >> + if (reg) { > >> + val = RST_READ(reg); > >> + val |= AR71XX_RESET_FULL_CHIP; > >> + RST_WRITE(reg, val); > > > > setbits_le32() please. > > Macro setbits_le32() is not available for MIPS architecture. You can always add them :) > Other, I don't think there is better in being so explicit and using > little-endian. I believe your register accesses should have correct endianness exactly beause mips can be both endian.
On 12/24/2015 11:12 PM, Marek Vasut wrote: > On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote: > > [...] > >>>> +LEAF(lowlevel_init) >>>> + /* These three WLAN_RESET will avoid original issue */ >>>> + li t3, 0x03 >>>> +1: >>>> + li t0, KSEG1ADDR(AR71XX_RESET_BASE) >>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>> + ori t1, t1, 0x0800 >>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>> + nop >>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>> + li t2, 0xfffff7ff >>>> + and t1, t1, t2 >>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>> + nop >>>> + addi t3, t3, -1 >>>> + bnez t3, 1b >>>> + nop >>> This should be also easy to rewrite into C , right ? >> C runtime environment is not available. >> C stack is not ready before DDR has initialized. > Just point the stack into a locked cacheline or some onchip RAM and there > you have a C runtime. That should be pretty easy :) How to lock cacheline? My guess is that cache memory may be use to map SPI flash at 0x9f000000 by ROM code. > [...] > >>>> +phys_size_t initdram(int board_type) >>>> +{ >>>> + uint8_t *addr, *p; >>>> + int i; >>>> + >>>> + ddr_tap_init(); >>>> + addr = (uint8_t *)KSEG1; >>>> + *addr = 0x77; >>>> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { >>>> + p += 0x1000000; >>>> + *p = i; >>>> + if (*addr != 0x77) >>>> + break; >>>> + } >>> What is this and how does it work ? >> Physical memory was mapped circularly for this chip. > Can you please expand on that ? I am not as deep in this chip as you are, > so please explain it to me in a bit more detail. > >>>> + return (phys_size_t)(p - addr); >>>> +} > [...] > >>>> + if (reg) { >>>> + val = RST_READ(reg); >>>> + val |= AR71XX_RESET_FULL_CHIP; >>>> + RST_WRITE(reg, val); >>> setbits_le32() please. >> Macro setbits_le32() is not available for MIPS architecture. > You can always add them :) > >> Other, I don't think there is better in being so explicit and using >> little-endian. > I believe your register accesses should have correct endianness exactly > beause mips can be both endian. > > What is the advantage of using setbits_le32()?
On Friday, December 25, 2015 at 12:38:39 PM, Wills Wang wrote: > On 12/24/2015 11:12 PM, Marek Vasut wrote: > > On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote: > > > > [...] > > > >>>> +LEAF(lowlevel_init) > >>>> + /* These three WLAN_RESET will avoid original issue */ > >>>> + li t3, 0x03 > >>>> +1: > >>>> + li t0, KSEG1ADDR(AR71XX_RESET_BASE) > >>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >>>> + ori t1, t1, 0x0800 > >>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >>>> + nop > >>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >>>> + li t2, 0xfffff7ff > >>>> + and t1, t1, t2 > >>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) > >>>> + nop > >>>> + addi t3, t3, -1 > >>>> + bnez t3, 1b > >>>> + nop > >>> > >>> This should be also easy to rewrite into C , right ? > >> > >> C runtime environment is not available. > >> C stack is not ready before DDR has initialized. > > > > Just point the stack into a locked cacheline or some onchip RAM and there > > you have a C runtime. That should be pretty easy :) > > How to lock cacheline? You'd have to check the MIPS core manual, I don't know the details, sorry. > My guess is that cache memory may be use to map SPI flash at 0x9f000000 > by ROM code. The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all. Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331. > > [...] > > > >>>> +phys_size_t initdram(int board_type) > >>>> +{ > >>>> + uint8_t *addr, *p; > >>>> + int i; > >>>> + > >>>> + ddr_tap_init(); > >>>> + addr = (uint8_t *)KSEG1; > >>>> + *addr = 0x77; > >>>> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { > >>>> + p += 0x1000000; > >>>> + *p = i; > >>>> + if (*addr != 0x77) > >>>> + break; > >>>> + } > >>> > >>> What is this and how does it work ? > >> > >> Physical memory was mapped circularly for this chip. > > > > Can you please expand on that ? I am not as deep in this chip as you are, > > so please explain it to me in a bit more detail. Well ... ? > >>>> + return (phys_size_t)(p - addr); > >>>> +} > > > > [...] > > > >>>> + if (reg) { > >>>> + val = RST_READ(reg); > >>>> + val |= AR71XX_RESET_FULL_CHIP; > >>>> + RST_WRITE(reg, val); > >>> > >>> setbits_le32() please. > >> > >> Macro setbits_le32() is not available for MIPS architecture. > > > > You can always add them :) > > > >> Other, I don't think there is better in being so explicit and using > >> little-endian. > > > > I believe your register accesses should have correct endianness exactly > > beause mips can be both endian. > > What is the advantage of using setbits_le32()? You don't have these constant repeating patterns of: var = read() var |= BIT write(var) It makes things a bit less confusing. Best regards, Marek Vasut
On 12/26/2015 02:02 PM, Marek Vasut wrote: > On Friday, December 25, 2015 at 12:38:39 PM, Wills Wang wrote: >> On 12/24/2015 11:12 PM, Marek Vasut wrote: >>> On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote: >>> >>> [...] >>> >>>>>> +LEAF(lowlevel_init) >>>>>> + /* These three WLAN_RESET will avoid original issue */ >>>>>> + li t3, 0x03 >>>>>> +1: >>>>>> + li t0, KSEG1ADDR(AR71XX_RESET_BASE) >>>>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>>>> + ori t1, t1, 0x0800 >>>>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>>>> + nop >>>>>> + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>>>> + li t2, 0xfffff7ff >>>>>> + and t1, t1, t2 >>>>>> + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) >>>>>> + nop >>>>>> + addi t3, t3, -1 >>>>>> + bnez t3, 1b >>>>>> + nop >>>>> This should be also easy to rewrite into C , right ? >>>> C runtime environment is not available. >>>> C stack is not ready before DDR has initialized. >>> Just point the stack into a locked cacheline or some onchip RAM and there >>> you have a C runtime. That should be pretty easy :) >> How to lock cacheline? > You'd have to check the MIPS core manual, I don't know the details, sorry. > >> My guess is that cache memory may be use to map SPI flash at 0x9f000000 >> by ROM code. > The SPI flash is an IP block which just maps the SPI NOR into the address space, > it doesn't use the CPU cache at all. > > Maybe you don't even need to lock cachelines though, the AR9331 should have some > internal SRAM, so just use that for stack. Do you have a proper datasheet for > the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331. I don't find any description about internal SRAM in public datasheet. About mapping SPI flash, there is a doubt, who fetch the instruction from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? I guess that ROM code handle cache exception and load instruction/date from SPI flash into cache. >>> [...] >>> >>>>>> +phys_size_t initdram(int board_type) >>>>>> +{ >>>>>> + uint8_t *addr, *p; >>>>>> + int i; >>>>>> + >>>>>> + ddr_tap_init(); >>>>>> + addr = (uint8_t *)KSEG1; >>>>>> + *addr = 0x77; >>>>>> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { >>>>>> + p += 0x1000000; >>>>>> + *p = i; >>>>>> + if (*addr != 0x77) >>>>>> + break; >>>>>> + } >>>>> What is this and how does it work ? >>>> Physical memory was mapped circularly for this chip. >>> Can you please expand on that ? I am not as deep in this chip as you are, >>> so please explain it to me in a bit more detail. > Well ... ? There is 64MB DDR on my board, the 64MB memory was mapped circularly into 0x00000000-0x03ffffff, 0x04000000-0x07ffffff, 0x08000000-0x0bffffff,... the address 0x00000000, 0x04000000 and 0x08000000 was mapped to the same physical memory. their corresponding KSEG1 address is 0xA0000000, 0xA4000000, 0xA8000000, when write a value into 0xA0000000, we can read the same value from address 0xA4000000 and 0xA8000000. > >>>>>> + return (phys_size_t)(p - addr); >>>>>> +} >>> [...] >>> >>>>>> + if (reg) { >>>>>> + val = RST_READ(reg); >>>>>> + val |= AR71XX_RESET_FULL_CHIP; >>>>>> + RST_WRITE(reg, val); >>>>> setbits_le32() please. >>>> Macro setbits_le32() is not available for MIPS architecture. >>> You can always add them :) >>> >>>> Other, I don't think there is better in being so explicit and using >>>> little-endian. >>> I believe your register accesses should have correct endianness exactly >>> beause mips can be both endian. >> What is the advantage of using setbits_le32()? > You don't have these constant repeating patterns of: > > var = read() > var |= BIT > write(var) > > It makes things a bit less confusing. ok, AR9331 use big-endian. > Best regards, > Marek Vasut > >
On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote: [...] > > The SPI flash is an IP block which just maps the SPI NOR into the address > > space, it doesn't use the CPU cache at all. > > > > Maybe you don't even need to lock cachelines though, the AR9331 should > > have some internal SRAM, so just use that for stack. Do you have a > > proper datasheet for the Atheros MIPS chips ? I have some 320 pages > > datasheet for AR9331. > > I don't find any description about internal SRAM in public datasheet. > About mapping SPI flash, there is a doubt, who fetch the instruction from > the SPI Nor flash to CPU pipe line when chip boot from SPI flash? > I guess that ROM code handle cache exception and load instruction/date from > SPI flash into cache. I just pulled out the SPI NOR from the Arduino Yun I have here and connected an FPGA with SPI NOR emulator in there. All the chip does is it issues the fastread opcode to the SPI NOR when it boots. It does the same thing if you access the 0x9f000000..0x9fxxxxxx address range from the ancient U-Boot 1.1.x. My impression is that the SPI NOR controller in the chip does a mapping between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. There is no caching involved in that, all of this is done internally in the SPI NOR block. The mips24kc core should support locking cache lines , so if the SRAM is not available, this would have to do. > >>> [...] > >>> > >>>>>> +phys_size_t initdram(int board_type) > >>>>>> +{ > >>>>>> + uint8_t *addr, *p; > >>>>>> + int i; > >>>>>> + > >>>>>> + ddr_tap_init(); > >>>>>> + addr = (uint8_t *)KSEG1; > >>>>>> + *addr = 0x77; > >>>>>> + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { > >>>>>> + p += 0x1000000; > >>>>>> + *p = i; > >>>>>> + if (*addr != 0x77) > >>>>>> + break; > >>>>>> + } > >>>>> > >>>>> What is this and how does it work ? > >>>> > >>>> Physical memory was mapped circularly for this chip. > >>> > >>> Can you please expand on that ? I am not as deep in this chip as you > >>> are, so please explain it to me in a bit more detail. > > > > Well ... ? > > There is 64MB DDR on my board, the 64MB memory was mapped circularly into > 0x00000000-0x03ffffff, 0x04000000-0x07ffffff, 0x08000000-0x0bffffff,... > the address 0x00000000, 0x04000000 and 0x08000000 was mapped to the same > physical memory. their corresponding KSEG1 address is 0xA0000000, > 0xA4000000, > 0xA8000000, when write a value into 0xA0000000, we can read the same value > from address 0xA4000000 and 0xA8000000. So this is some sort of poor man's memory size detection mechanism ? See common/memsize.c , function get_ram_size() . That might help instead. > >>>>>> + return (phys_size_t)(p - addr); > >>>>>> +} > >>> > >>> [...] > >>> > >>>>>> + if (reg) { > >>>>>> + val = RST_READ(reg); > >>>>>> + val |= AR71XX_RESET_FULL_CHIP; > >>>>>> + RST_WRITE(reg, val); > >>>>> > >>>>> setbits_le32() please. > >>>> > >>>> Macro setbits_le32() is not available for MIPS architecture. > >>> > >>> You can always add them :) > >>> > >>>> Other, I don't think there is better in being so explicit and using > >>>> little-endian. > >>> > >>> I believe your register accesses should have correct endianness exactly > >>> beause mips can be both endian. > >> > >> What is the advantage of using setbits_le32()? > > > > You don't have these constant repeating patterns of: > > > > var = read() > > var |= BIT > > write(var) > > > > It makes things a bit less confusing. > > ok, AR9331 use big-endian. setbits_be32() then, same thing.
On Saturday, December 26, 2015 at 06:35:35 PM, Marek Vasut wrote: > On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote: > > [...] > > > > The SPI flash is an IP block which just maps the SPI NOR into the > > > address space, it doesn't use the CPU cache at all. > > > > > > Maybe you don't even need to lock cachelines though, the AR9331 should > > > have some internal SRAM, so just use that for stack. Do you have a > > > proper datasheet for the Atheros MIPS chips ? I have some 320 pages > > > datasheet for AR9331. > > > > I don't find any description about internal SRAM in public datasheet. > > About mapping SPI flash, there is a doubt, who fetch the instruction from > > the SPI Nor flash to CPU pipe line when chip boot from SPI flash? > > I guess that ROM code handle cache exception and load instruction/date > > from SPI flash into cache. > > I just pulled out the SPI NOR from the Arduino Yun I have here and > connected an FPGA with SPI NOR emulator in there. All the chip does is it > issues the fastread opcode to the SPI NOR when it boots. It does the same > thing if you access the 0x9f000000..0x9fxxxxxx address range from the > ancient U-Boot 1.1.x. > > My impression is that the SPI NOR controller in the chip does a mapping > between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. > There is no caching involved in that, all of this is done internally in > the SPI NOR block. > > The mips24kc core should support locking cache lines , so if the SRAM is > not available, this would have to do. Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this location out (thanks!) [1] https://github.com/pepe2k/u-boot_mod/blob/master/u- boot/cpu/mips/start.S#L652 Best regards, Marek Vasut
WASP is ar9341. On 12/27/2015 02:17 AM, Marek Vasut wrote: > On Saturday, December 26, 2015 at 06:35:35 PM, Marek Vasut wrote: >> On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote: >> >> [...] >> >>>> The SPI flash is an IP block which just maps the SPI NOR into the >>>> address space, it doesn't use the CPU cache at all. >>>> >>>> Maybe you don't even need to lock cachelines though, the AR9331 should >>>> have some internal SRAM, so just use that for stack. Do you have a >>>> proper datasheet for the Atheros MIPS chips ? I have some 320 pages >>>> datasheet for AR9331. >>> I don't find any description about internal SRAM in public datasheet. >>> About mapping SPI flash, there is a doubt, who fetch the instruction from >>> the SPI Nor flash to CPU pipe line when chip boot from SPI flash? >>> I guess that ROM code handle cache exception and load instruction/date >>> from SPI flash into cache. >> I just pulled out the SPI NOR from the Arduino Yun I have here and >> connected an FPGA with SPI NOR emulator in there. All the chip does is it >> issues the fastread opcode to the SPI NOR when it boots. It does the same >> thing if you access the 0x9f000000..0x9fxxxxxx address range from the >> ancient U-Boot 1.1.x. >> >> My impression is that the SPI NOR controller in the chip does a mapping >> between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. >> There is no caching involved in that, all of this is done internally in >> the SPI NOR block. >> >> The mips24kc core should support locking cache lines , so if the SRAM is >> not available, this would have to do. > Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this location > out (thanks!) > > [1] https://github.com/pepe2k/u-boot_mod/blob/master/u- > boot/cpu/mips/start.S#L652 > > Best regards, > Marek Vasut > >
On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > WASP is ar9341. Please do not top post. Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] . > On 12/27/2015 02:17 AM, Marek Vasut wrote: > > On Saturday, December 26, 2015 at 06:35:35 PM, Marek Vasut wrote: > >> On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote: > >> > >> [...] > >> > >>>> The SPI flash is an IP block which just maps the SPI NOR into the > >>>> address space, it doesn't use the CPU cache at all. > >>>> > >>>> Maybe you don't even need to lock cachelines though, the AR9331 should > >>>> have some internal SRAM, so just use that for stack. Do you have a > >>>> proper datasheet for the Atheros MIPS chips ? I have some 320 pages > >>>> datasheet for AR9331. > >>> > >>> I don't find any description about internal SRAM in public datasheet. > >>> About mapping SPI flash, there is a doubt, who fetch the instruction > >>> from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? > >>> I guess that ROM code handle cache exception and load instruction/date > >>> from SPI flash into cache. > >> > >> I just pulled out the SPI NOR from the Arduino Yun I have here and > >> connected an FPGA with SPI NOR emulator in there. All the chip does is > >> it issues the fastread opcode to the SPI NOR when it boots. It does the > >> same thing if you access the 0x9f000000..0x9fxxxxxx address range from > >> the ancient U-Boot 1.1.x. > >> > >> My impression is that the SPI NOR controller in the chip does a mapping > >> between the SPI NOR and the memory mapped access to the 0x9fxxxxxx > >> range. There is no caching involved in that, all of this is done > >> internally in the SPI NOR block. > >> > >> The mips24kc core should support locking cache lines , so if the SRAM is > >> not available, this would have to do. > > > > Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this > > location out (thanks!) > > > > [1] https://github.com/pepe2k/u-boot_mod/blob/master/u- > > boot/cpu/mips/start.S#L652 > > > > Best regards, > > Marek Vasut Best regards, Marek Vasut
On 12/27/2015 02:37 AM, Marek Vasut wrote: > On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >> WASP is ar9341. > Please do not top post. > > Did you try if the memory is accessible on your platform ? AR9331 I have here > has the SRAM at 0xbd007000 , just like that machine in [1] . I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. Best Regards Wills
On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: > On 12/27/2015 02:37 AM, Marek Vasut wrote: > > On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > >> WASP is ar9341. > > > > Please do not top post. > > > > Did you try if the memory is accessible on your platform ? AR9331 I have > > here has the SRAM at 0xbd007000 , just like that machine in [1] . > > I found there is a memory segment at 0xbd000000...0xbd007fff. it's > independent of DDR physical memory, can be read and wrote, but > hardware can't boot up if don't execute lowlevel_init.S when define > CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000. Best regards, Marek Vasut
On 12/27/2015 03:38 PM, Marek Vasut wrote: > On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>> WASP is ar9341. >>> Please do not top post. >>> >>> Did you try if the memory is accessible on your platform ? AR9331 I have >>> here has the SRAM at 0xbd007000 , just like that machine in [1] . >> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >> independent of DDR physical memory, can be read and wrote, but >> hardware can't boot up if don't execute lowlevel_init.S when define >> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. > Stack grows down, so of course if you put stack at the beginning of SRAM, > that cannot work ;-) Put it at the end , 0xbd008000. This memory segment was mapped circularly at 0xbd000000...0xbdffffff. > Best regards, > Marek Vasut > >
On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: > On 12/27/2015 03:38 PM, Marek Vasut wrote: > > On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: > >> On 12/27/2015 02:37 AM, Marek Vasut wrote: > >>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > >>>> WASP is ar9341. > >>> > >>> Please do not top post. > >>> > >>> Did you try if the memory is accessible on your platform ? AR9331 I > >>> have here has the SRAM at 0xbd007000 , just like that machine in [1] . > >> > >> I found there is a memory segment at 0xbd000000...0xbd007fff. it's > >> independent of DDR physical memory, can be read and wrote, but > >> hardware can't boot up if don't execute lowlevel_init.S when define > >> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. > > > > Stack grows down, so of course if you put stack at the beginning of SRAM, > > that cannot work ;-) Put it at the end , 0xbd008000. > > This memory segment was mapped circularly at 0xbd000000...0xbdffffff. So is this area at 0xbd008000 usable for stack or not ? Best regards, Marek Vasut
On 12/27/2015 06:09 PM, Marek Vasut wrote: > On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: >> On 12/27/2015 03:38 PM, Marek Vasut wrote: >>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>>>> WASP is ar9341. >>>>> Please do not top post. >>>>> >>>>> Did you try if the memory is accessible on your platform ? AR9331 I >>>>> have here has the SRAM at 0xbd007000 , just like that machine in [1] . >>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >>>> independent of DDR physical memory, can be read and wrote, but >>>> hardware can't boot up if don't execute lowlevel_init.S when define >>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. >>> Stack grows down, so of course if you put stack at the beginning of SRAM, >>> that cannot work ;-) Put it at the end , 0xbd008000. >> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. > So is this area at 0xbd008000 usable for stack or not ? Same times board can boot up, but in a very unstable. i use the following setting: #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > Best regards, > Marek Vasut > >
On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: > On 12/27/2015 06:09 PM, Marek Vasut wrote: > > On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: > >> On 12/27/2015 03:38 PM, Marek Vasut wrote: > >>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: > >>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: > >>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > >>>>>> WASP is ar9341. > >>>>> > >>>>> Please do not top post. > >>>>> > >>>>> Did you try if the memory is accessible on your platform ? AR9331 I > >>>>> have here has the SRAM at 0xbd007000 , just like that machine in [1] > >>>>> . > >>>> > >>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's > >>>> independent of DDR physical memory, can be read and wrote, but > >>>> hardware can't boot up if don't execute lowlevel_init.S when define > >>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. > >>> > >>> Stack grows down, so of course if you put stack at the beginning of > >>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. > >> > >> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. > > > > So is this area at 0xbd008000 usable for stack or not ? > > Same times board can boot up, but in a very unstable. i use the > following setting: > > #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 Should be 0xbd007000 > #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) Should be 4 KiB large. > #define CONFIG_SYS_INIT_SP_OFFSET \ > (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > #define CONFIG_SYS_INIT_SP_ADDR \ > (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) Did you investigate why the board has problems ? Best regards, Marek Vasut
On 12/27/2015 07:04 PM, Marek Vasut wrote: > On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: >> On 12/27/2015 06:09 PM, Marek Vasut wrote: >>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: >>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: >>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>>>>>> WASP is ar9341. >>>>>>> Please do not top post. >>>>>>> >>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I >>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in [1] >>>>>>> . >>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >>>>>> independent of DDR physical memory, can be read and wrote, but >>>>>> hardware can't boot up if don't execute lowlevel_init.S when define >>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. >>>>> Stack grows down, so of course if you put stack at the beginning of >>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. >>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. >>> So is this area at 0xbd008000 usable for stack or not ? >> Same times board can boot up, but in a very unstable. i use the >> following setting: >> >> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > Should be 0xbd007000 > >> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > Should be 4 KiB large. > >> #define CONFIG_SYS_INIT_SP_OFFSET \ >> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) >> #define CONFIG_SYS_INIT_SP_ADDR \ >> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > Did you investigate why the board has problems ? "lowlevel_init.S" can't be dropped. > > Best regards, > Marek Vasut > >
Am 27.12.2015 um 12:04 schrieb Marek Vasut: > On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: >> On 12/27/2015 06:09 PM, Marek Vasut wrote: >>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: >>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: >>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>>>>>> WASP is ar9341. >>>>>>> >>>>>>> Please do not top post. >>>>>>> >>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I >>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in [1] >>>>>>> . >>>>>> >>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >>>>>> independent of DDR physical memory, can be read and wrote, but >>>>>> hardware can't boot up if don't execute lowlevel_init.S when define >>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. >>>>> >>>>> Stack grows down, so of course if you put stack at the beginning of >>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. >>>> >>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. >>> >>> So is this area at 0xbd008000 usable for stack or not ? >> >> Same times board can boot up, but in a very unstable. i use the >> following setting: >> >> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > > Should be 0xbd007000 > >> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > > Should be 4 KiB large. > >> #define CONFIG_SYS_INIT_SP_OFFSET \ >> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) >> #define CONFIG_SYS_INIT_SP_ADDR \ >> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > Did you investigate why the board has problems ? > according to the description above by Wills those three defines setup the values correctly for start.S: #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) The stack pointer will then be set to the end of the SRAM area with a 16 Byte alignment. The resulting address should be 0xbd007ff0. From this address, the size of gd_t and CONFIG_SYS_MALLOC_F_LEN will be subtracted. The remaining space is available for the initial stack. Which value did you chose for CONFIG_SYS_MALLOC_F_LEN? It must be big enough to satisfy all malloc requests by the DM stack and small enough to fit in 32k minus stack size and gd_t size. Important note: do net set CONFIG_SKIP_LOWLEVEL_INIT yet because that leaves you without initialized RAM or caches. If the setup does not work yet, you likely need to init some extra bits to make the SRAM working.
On Sunday, December 27, 2015 at 12:37:37 PM, Daniel Schwierzeck wrote: > Am 27.12.2015 um 12:04 schrieb Marek Vasut: > > On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: > >> On 12/27/2015 06:09 PM, Marek Vasut wrote: > >>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: > >>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: > >>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: > >>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: > >>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > >>>>>>>> WASP is ar9341. > >>>>>>> > >>>>>>> Please do not top post. > >>>>>>> > >>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I > >>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in > >>>>>>> [1] . > >>>>>> > >>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's > >>>>>> independent of DDR physical memory, can be read and wrote, but > >>>>>> hardware can't boot up if don't execute lowlevel_init.S when define > >>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. > >>>>> > >>>>> Stack grows down, so of course if you put stack at the beginning of > >>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. > >>>> > >>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. > >>> > >>> So is this area at 0xbd008000 usable for stack or not ? > >> > >> Same times board can boot up, but in a very unstable. i use the > >> following setting: > >> > >> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > > > > Should be 0xbd007000 > > > >> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > > > > Should be 4 KiB large. > > > >> #define CONFIG_SYS_INIT_SP_OFFSET \ > >> > >> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > >> > >> #define CONFIG_SYS_INIT_SP_ADDR \ > >> > >> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > > > Did you investigate why the board has problems ? > > according to the description above by Wills those three defines setup > the values correctly for start.S: > > #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > #define CONFIG_SYS_INIT_SP_ADDR \ > (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) > > The stack pointer will then be set to the end of the SRAM area with a 16 > Byte alignment. The resulting address should be 0xbd007ff0. From this > address, the size of gd_t and CONFIG_SYS_MALLOC_F_LEN will be > subtracted. The remaining space is available for the initial stack. > > Which value did you chose for CONFIG_SYS_MALLOC_F_LEN? It must be big > enough to satisfy all malloc requests by the DM stack and small enough > to fit in 32k minus stack size and gd_t size. Careful about those 32k, I think the code which I referenced only uses 4k area. > Important note: do net set CONFIG_SKIP_LOWLEVEL_INIT yet because that > leaves you without initialized RAM or caches. If the setup does not work > yet, you likely need to init some extra bits to make the SRAM working. Best regards,
On Sunday, December 27, 2015 at 12:37:16 PM, Wills Wang wrote: > On 12/27/2015 07:04 PM, Marek Vasut wrote: > > On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: > >> On 12/27/2015 06:09 PM, Marek Vasut wrote: > >>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: > >>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: > >>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: > >>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: > >>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: > >>>>>>>> WASP is ar9341. > >>>>>>> > >>>>>>> Please do not top post. > >>>>>>> > >>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I > >>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in > >>>>>>> [1] . > >>>>>> > >>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's > >>>>>> independent of DDR physical memory, can be read and wrote, but > >>>>>> hardware can't boot up if don't execute lowlevel_init.S when define > >>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. > >>>>> > >>>>> Stack grows down, so of course if you put stack at the beginning of > >>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. > >>>> > >>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. > >>> > >>> So is this area at 0xbd008000 usable for stack or not ? > >> > >> Same times board can boot up, but in a very unstable. i use the > >> following setting: > >> > >> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > > > > Should be 0xbd007000 > > > >> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > > > > Should be 4 KiB large. > > > >> #define CONFIG_SYS_INIT_SP_OFFSET \ > >> > >> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > >> > >> #define CONFIG_SYS_INIT_SP_ADDR \ > >> > >> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > > > Did you investigate why the board has problems ? > > "lowlevel_init.S" can't be dropped. Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed. Best regards, Marek Vasut
On 12/27/2015 07:37 PM, Daniel Schwierzeck wrote: > > Am 27.12.2015 um 12:04 schrieb Marek Vasut: >> On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: >>> On 12/27/2015 06:09 PM, Marek Vasut wrote: >>>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: >>>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: >>>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >>>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>>>>>>> WASP is ar9341. >>>>>>>> Please do not top post. >>>>>>>> >>>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I >>>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in [1] >>>>>>>> . >>>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >>>>>>> independent of DDR physical memory, can be read and wrote, but >>>>>>> hardware can't boot up if don't execute lowlevel_init.S when define >>>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. >>>>>> Stack grows down, so of course if you put stack at the beginning of >>>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. >>>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. >>>> So is this area at 0xbd008000 usable for stack or not ? >>> Same times board can boot up, but in a very unstable. i use the >>> following setting: >>> >>> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 >> Should be 0xbd007000 >> >>> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) >> Should be 4 KiB large. >> >>> #define CONFIG_SYS_INIT_SP_OFFSET \ >>> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) >>> #define CONFIG_SYS_INIT_SP_ADDR \ >>> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) >> Did you investigate why the board has problems ? >> > according to the description above by Wills those three defines setup > the values correctly for start.S: > > #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 > #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) > #define CONFIG_SYS_INIT_SP_ADDR \ > (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) > > The stack pointer will then be set to the end of the SRAM area with a 16 > Byte alignment. The resulting address should be 0xbd007ff0. From this > address, the size of gd_t and CONFIG_SYS_MALLOC_F_LEN will be > subtracted. The remaining space is available for the initial stack. > > Which value did you chose for CONFIG_SYS_MALLOC_F_LEN? It must be big > enough to satisfy all malloc requests by the DM stack and small enough > to fit in 32k minus stack size and gd_t size. > > Important note: do net set CONFIG_SKIP_LOWLEVEL_INIT yet because that > leaves you without initialized RAM or caches. If the setup does not work > yet, you likely need to init some extra bits to make the SRAM working. > #define CONFIG_SYS_MALLOC_F_LEN 0x2000 I don't set CONFIG_SKIP_LOWLEVEL_INIT
On 12/27/2015 08:27 PM, Marek Vasut wrote: > On Sunday, December 27, 2015 at 12:37:16 PM, Wills Wang wrote: >> On 12/27/2015 07:04 PM, Marek Vasut wrote: >>> On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote: >>>> On 12/27/2015 06:09 PM, Marek Vasut wrote: >>>>> On Sunday, December 27, 2015 at 09:07:36 AM, Wills Wang wrote: >>>>>> On 12/27/2015 03:38 PM, Marek Vasut wrote: >>>>>>> On Sunday, December 27, 2015 at 08:33:26 AM, Wills Wang wrote: >>>>>>>> On 12/27/2015 02:37 AM, Marek Vasut wrote: >>>>>>>>> On Saturday, December 26, 2015 at 07:29:51 PM, Wills Wang wrote: >>>>>>>>>> WASP is ar9341. >>>>>>>>> Please do not top post. >>>>>>>>> >>>>>>>>> Did you try if the memory is accessible on your platform ? AR9331 I >>>>>>>>> have here has the SRAM at 0xbd007000 , just like that machine in >>>>>>>>> [1] . >>>>>>>> I found there is a memory segment at 0xbd000000...0xbd007fff. it's >>>>>>>> independent of DDR physical memory, can be read and wrote, but >>>>>>>> hardware can't boot up if don't execute lowlevel_init.S when define >>>>>>>> CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM. >>>>>>> Stack grows down, so of course if you put stack at the beginning of >>>>>>> SRAM, that cannot work ;-) Put it at the end , 0xbd008000. >>>>>> This memory segment was mapped circularly at 0xbd000000...0xbdffffff. >>>>> So is this area at 0xbd008000 usable for stack or not ? >>>> Same times board can boot up, but in a very unstable. i use the >>>> following setting: >>>> >>>> #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 >>> Should be 0xbd007000 >>> >>>> #define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K) >>> Should be 4 KiB large. >>> >>>> #define CONFIG_SYS_INIT_SP_OFFSET \ >>>> >>>> (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) >>>> >>>> #define CONFIG_SYS_INIT_SP_ADDR \ >>>> >>>> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) >>> Did you investigate why the board has problems ? >> "lowlevel_init.S" can't be dropped. > Thank you very much for all the effort you put into investigating and explaining > why this SRAM area cannot be used ... not. From my side, consider this patch to > be NAKed. > > Best regards, > Marek Vasut > > "lowlevel_init.S" can't be entirely dropped, there are three main reasons for this. 1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up. 2. Need reset RTC and force to wake MAC, or chip can't work . 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from power-up to printout is about 5s. So, assembler code could not be avoided even using SRAM for c stack. Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think that using DDR should be more consolidated.
On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: [...] > >> "lowlevel_init.S" can't be dropped. > > > > Thank you very much for all the effort you put into investigating and > > explaining why this SRAM area cannot be used ... not. From my side, > > consider this patch to be NAKed. > > > > Best regards, > > Marek Vasut > > "lowlevel_init.S" can't be entirely dropped, there are three main > reasons for this. Right, so I checked how these are performed and whether these can or cannot be done from C code. > 1. Chip has an original issue, need reset "WLAN" three times to avoid > it when power up. 26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */ 28 set_reg(0xb806001c, 0x00c06b30) 29 nop 30 set_reg(0xb806001c, 0x00c06330) 31 nop 32 set_reg(0xb806001c, 0x00c06b30) 33 nop 34 set_reg(0xb806001c, 0x00c06330) 35 nop 36 reset_wlan: 37 set_reg(0xb806001c, 0x00c06b30) 38 nop 39 set_reg(0xb806001c, 0x00c06330) 40 nop Yes, these can be done from C code. > 2. Need reset RTC and force to wake MAC, or chip can't work . 73 /* RTC reset */ 74 set_reg(0x1810704c, 0x00000003) 75 nop 76 nop 77 set_reg(0x18107040, 0x00000000) 78 nop 79 nop 80 set_reg(0x18107040, 0x00000001) 81 nop DTTO. > 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is > 25MHz, the interval from > power-up to printout is about 5s. The PLL configuration is again a set of writes to some random registers. This can again be done from the C code. > So, assembler code could not be avoided even using SRAM for c stack. I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it. > Now that chipmaker don't open SRAM of this chip and recommend DDR for > initial stack, i think > that using DDR should be more consolidated. I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers. So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be. Best regards, Marek Vasut
On 12/28/2015 09:47 PM, Marek Vasut wrote: > On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: > [...] >>>> "lowlevel_init.S" can't be dropped. >>> Thank you very much for all the effort you put into investigating and >>> explaining why this SRAM area cannot be used ... not. From my side, >>> consider this patch to be NAKed. >>> >>> Best regards, >>> Marek Vasut >> "lowlevel_init.S" can't be entirely dropped, there are three main >> reasons for this. > Right, so I checked how these are performed and whether these can or cannot > be done from C code. > >> 1. Chip has an original issue, need reset "WLAN" three times to avoid >> it when power up. > 26 /* These three wlan reset will avoid original issue, > 27 so full chip reset isn't needed here. */ > 28 set_reg(0xb806001c, 0x00c06b30) > 29 nop > 30 set_reg(0xb806001c, 0x00c06330) > 31 nop > 32 set_reg(0xb806001c, 0x00c06b30) > 33 nop > 34 set_reg(0xb806001c, 0x00c06330) > 35 nop > 36 reset_wlan: > 37 set_reg(0xb806001c, 0x00c06b30) > 38 nop > 39 set_reg(0xb806001c, 0x00c06330) > 40 nop > > Yes, these can be done from C code. > >> 2. Need reset RTC and force to wake MAC, or chip can't work . > 73 /* RTC reset */ > 74 set_reg(0x1810704c, 0x00000003) > 75 nop > 76 nop > 77 set_reg(0x18107040, 0x00000000) > 78 nop > 79 nop > 80 set_reg(0x18107040, 0x00000001) > 81 nop > > DTTO. > >> 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is >> 25MHz, the interval from >> power-up to printout is about 5s. > The PLL configuration is again a set of writes to some random registers. > This can again be done from the C code. > >> So, assembler code could not be avoided even using SRAM for c stack. > I am not convinced, see above. Please show me where exactly is the assembly > code imperative. I simply do not see it. > >> Now that chipmaker don't open SRAM of this chip and recommend DDR for >> initial stack, i think >> that using DDR should be more consolidated. > I do not care what the chip maker says unless there is an explicit explanation > why they require that. Most often, these sorts of "limitations" are in place > only because the chipmaker has incompetent software engineers. > > So I would like to see either the SRAM or locked cacheline used for stack and > then lowlevel init converted into proper C code unless there is an explicit > explanation why this can not be done. And by explicit I mean for example a > snippet of code which cannot be converted into C code. Note that asm volatile > can still be used to contain such small bits of assembler code if needed be. > > Best regards, > Marek Vasut > > I made a series of tries in this, and i can confirm that the SRAM can be used for c stack, but the prerequisites for this are that the above two points (1&2) must be execute in lowlevel_init. i has converted these code to C, and put them(1&2) at arch_cpu_init, but hardware don't work, i guess that these parts may be associated with memory submodule of this chip.
On 12/28/2015 09:47 PM, Marek Vasut wrote: > On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: > [...] >>>> "lowlevel_init.S" can't be dropped. >>> Thank you very much for all the effort you put into investigating and >>> explaining why this SRAM area cannot be used ... not. From my side, >>> consider this patch to be NAKed. >>> >>> Best regards, >>> Marek Vasut >> "lowlevel_init.S" can't be entirely dropped, there are three main >> reasons for this. > Right, so I checked how these are performed and whether these can or cannot > be done from C code. > >> 1. Chip has an original issue, need reset "WLAN" three times to avoid >> it when power up. > 26 /* These three wlan reset will avoid original issue, > 27 so full chip reset isn't needed here. */ > 28 set_reg(0xb806001c, 0x00c06b30) > 29 nop > 30 set_reg(0xb806001c, 0x00c06330) > 31 nop > 32 set_reg(0xb806001c, 0x00c06b30) > 33 nop > 34 set_reg(0xb806001c, 0x00c06330) > 35 nop > 36 reset_wlan: > 37 set_reg(0xb806001c, 0x00c06b30) > 38 nop > 39 set_reg(0xb806001c, 0x00c06330) > 40 nop > > Yes, these can be done from C code. > >> 2. Need reset RTC and force to wake MAC, or chip can't work . > 73 /* RTC reset */ > 74 set_reg(0x1810704c, 0x00000003) > 75 nop > 76 nop > 77 set_reg(0x18107040, 0x00000000) > 78 nop > 79 nop > 80 set_reg(0x18107040, 0x00000001) > 81 nop > > DTTO. > >> 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is >> 25MHz, the interval from >> power-up to printout is about 5s. > The PLL configuration is again a set of writes to some random registers. > This can again be done from the C code. > >> So, assembler code could not be avoided even using SRAM for c stack. > I am not convinced, see above. Please show me where exactly is the assembly > code imperative. I simply do not see it. > >> Now that chipmaker don't open SRAM of this chip and recommend DDR for >> initial stack, i think >> that using DDR should be more consolidated. > I do not care what the chip maker says unless there is an explicit explanation > why they require that. Most often, these sorts of "limitations" are in place > only because the chipmaker has incompetent software engineers. > > So I would like to see either the SRAM or locked cacheline used for stack and > then lowlevel init converted into proper C code unless there is an explicit > explanation why this can not be done. And by explicit I mean for example a > snippet of code which cannot be converted into C code. Note that asm volatile > can still be used to contain such small bits of assembler code if needed be. > > Best regards, > Marek Vasut > > I made a series of tries in this, i configure initial stack in SRAM and convert these code to c, and put them in arch_cpu_init(the first available c entry), but hardware don't work. if i keep the above three points(RESET/RTC/PLL) in lowlevel_init, put other code in arch_cpu_init, board work fine.
On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote: > On 12/28/2015 09:47 PM, Marek Vasut wrote: > > On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: > > [...] > > > >>>> "lowlevel_init.S" can't be dropped. > >>> > >>> Thank you very much for all the effort you put into investigating and > >>> explaining why this SRAM area cannot be used ... not. From my side, > >>> consider this patch to be NAKed. > >>> > >>> Best regards, > >>> Marek Vasut > >> > >> "lowlevel_init.S" can't be entirely dropped, there are three main > >> reasons for this. > > > > Right, so I checked how these are performed and whether these can or > > cannot be done from C code. > > > >> 1. Chip has an original issue, need reset "WLAN" three times to avoid > >> it when power up. > >> > > 26 /* These three wlan reset will avoid original issue, > > 27 so full chip reset isn't needed here. */ > > 28 set_reg(0xb806001c, 0x00c06b30) > > 29 nop > > 30 set_reg(0xb806001c, 0x00c06330) > > 31 nop > > 32 set_reg(0xb806001c, 0x00c06b30) > > 33 nop > > 34 set_reg(0xb806001c, 0x00c06330) > > 35 nop > > 36 reset_wlan: > > 37 set_reg(0xb806001c, 0x00c06b30) > > 38 nop > > 39 set_reg(0xb806001c, 0x00c06330) > > 40 nop > > > > Yes, these can be done from C code. > > > >> 2. Need reset RTC and force to wake MAC, or chip can't work . > >> > > 73 /* RTC reset */ > > 74 set_reg(0x1810704c, 0x00000003) > > 75 nop > > 76 nop > > 77 set_reg(0x18107040, 0x00000000) > > 78 nop > > 79 nop > > 80 set_reg(0x18107040, 0x00000001) > > 81 nop > > > > DTTO. > > > >> 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is > >> 25MHz, the interval from > >> power-up to printout is about 5s. > > > > The PLL configuration is again a set of writes to some random registers. > > This can again be done from the C code. > > > >> So, assembler code could not be avoided even using SRAM for c stack. > > > > I am not convinced, see above. Please show me where exactly is the > > assembly code imperative. I simply do not see it. > > > >> Now that chipmaker don't open SRAM of this chip and recommend DDR for > >> initial stack, i think > >> that using DDR should be more consolidated. > > > > I do not care what the chip maker says unless there is an explicit > > explanation why they require that. Most often, these sorts of > > "limitations" are in place only because the chipmaker has incompetent > > software engineers. > > > > So I would like to see either the SRAM or locked cacheline used for stack > > and then lowlevel init converted into proper C code unless there is an > > explicit explanation why this can not be done. And by explicit I mean > > for example a snippet of code which cannot be converted into C code. > > Note that asm volatile can still be used to contain such small bits of > > assembler code if needed be. > > > > Best regards, > > Marek Vasut > > I made a series of tries in this, i configure initial stack in SRAM and > convert > these code to c, and put them in arch_cpu_init(the first available c > entry), but > hardware don't work. if i keep the above three points(RESET/RTC/PLL) in > lowlevel_init, put other code in arch_cpu_init, board work fine. So let me ask the question again -- why does the C code not work ? Did you investigate the reason why does the C code not work ? Can you share the change you did to convert things to C code ? There might be a bug in that too ...
Am 28.12.2015 um 16:52 schrieb Marek Vasut: > On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote: >> On 12/28/2015 09:47 PM, Marek Vasut wrote: >>> On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: >>> [...] >>> >>>>>> "lowlevel_init.S" can't be dropped. >>>>> >>>>> Thank you very much for all the effort you put into investigating and >>>>> explaining why this SRAM area cannot be used ... not. From my side, >>>>> consider this patch to be NAKed. >>>>> >>>>> Best regards, >>>>> Marek Vasut >>>> >>>> "lowlevel_init.S" can't be entirely dropped, there are three main >>>> reasons for this. >>> >>> Right, so I checked how these are performed and whether these can or >>> cannot be done from C code. >>> >>>> 1. Chip has an original issue, need reset "WLAN" three times to avoid >>>> it when power up. >>>> >>> 26 /* These three wlan reset will avoid original issue, >>> 27 so full chip reset isn't needed here. */ >>> 28 set_reg(0xb806001c, 0x00c06b30) >>> 29 nop >>> 30 set_reg(0xb806001c, 0x00c06330) >>> 31 nop >>> 32 set_reg(0xb806001c, 0x00c06b30) >>> 33 nop >>> 34 set_reg(0xb806001c, 0x00c06330) >>> 35 nop >>> 36 reset_wlan: >>> 37 set_reg(0xb806001c, 0x00c06b30) >>> 38 nop >>> 39 set_reg(0xb806001c, 0x00c06330) >>> 40 nop >>> >>> Yes, these can be done from C code. >>> >>>> 2. Need reset RTC and force to wake MAC, or chip can't work . >>>> >>> 73 /* RTC reset */ >>> 74 set_reg(0x1810704c, 0x00000003) >>> 75 nop >>> 76 nop >>> 77 set_reg(0x18107040, 0x00000000) >>> 78 nop >>> 79 nop >>> 80 set_reg(0x18107040, 0x00000001) >>> 81 nop >>> >>> DTTO. >>> >>>> 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is >>>> 25MHz, the interval from >>>> power-up to printout is about 5s. >>> >>> The PLL configuration is again a set of writes to some random registers. >>> This can again be done from the C code. >>> >>>> So, assembler code could not be avoided even using SRAM for c stack. >>> >>> I am not convinced, see above. Please show me where exactly is the >>> assembly code imperative. I simply do not see it. >>> >>>> Now that chipmaker don't open SRAM of this chip and recommend DDR for >>>> initial stack, i think >>>> that using DDR should be more consolidated. >>> >>> I do not care what the chip maker says unless there is an explicit >>> explanation why they require that. Most often, these sorts of >>> "limitations" are in place only because the chipmaker has incompetent >>> software engineers. >>> >>> So I would like to see either the SRAM or locked cacheline used for stack >>> and then lowlevel init converted into proper C code unless there is an >>> explicit explanation why this can not be done. And by explicit I mean >>> for example a snippet of code which cannot be converted into C code. >>> Note that asm volatile can still be used to contain such small bits of >>> assembler code if needed be. >>> >>> Best regards, >>> Marek Vasut >> >> I made a series of tries in this, i configure initial stack in SRAM and >> convert >> these code to c, and put them in arch_cpu_init(the first available c >> entry), but >> hardware don't work. if i keep the above three points(RESET/RTC/PLL) in >> lowlevel_init, put other code in arch_cpu_init, board work fine. > > So let me ask the question again -- why does the C code not work ? Did you > investigate the reason why does the C code not work ? > > Can you share the change you did to convert things to C code ? There might > be a bug in that too ... > it is not a matter of C or assembly, but of the init sequence currently implemented on MIPS. The main purpose of lowlevel_init() is to initialize memory controllers and DRAM. This has to be done in assembly because we have no C runtime environment available at that point. Also compiling U-Boot as PIC requires to enable MIPS ABI function calls in gcc (-mabicalls). This always creates function prologues and epilogues which are utilizing the stack pointer. Thus we cannot simply convert all lowlevel_init functions to C. Moving code from lowlevel_init to arch_cpu_init or elsewhere will not work because that code runs too late then. Simply moving the stack to SRAM will also not help because lowlevel_init runs before the stack is available. Before Wills can convert his code to C, we need to rework the init sequence in start.S. But that is out of the scope of this patch series. I will try to prepare some patches in the next days. The SRAM part should be easy. But the cache line lock need some more work and testing. In the meantime Wills could send a new patch series, which addresses all other issues except lowlevel_init. The function ddr_tap_init can be already converted to C because it is called from init_dram where a C runtime environment is available. So we could have at least a working patch series and could finalize the review of the other patches. After I have updated u-boot-mips/next branch, Wills can rebase and convert lowlevel_init to C.
On Monday, December 28, 2015 at 06:08:52 PM, Daniel Schwierzeck wrote: > Am 28.12.2015 um 16:52 schrieb Marek Vasut: > > On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote: > >> On 12/28/2015 09:47 PM, Marek Vasut wrote: > >>> On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote: > >>> [...] > >>> > >>>>>> "lowlevel_init.S" can't be dropped. > >>>>> > >>>>> Thank you very much for all the effort you put into investigating and > >>>>> explaining why this SRAM area cannot be used ... not. From my side, > >>>>> consider this patch to be NAKed. > >>>>> > >>>>> Best regards, > >>>>> Marek Vasut > >>>> > >>>> "lowlevel_init.S" can't be entirely dropped, there are three main > >>>> reasons for this. > >>> > >>> Right, so I checked how these are performed and whether these can or > >>> cannot be done from C code. > >>> > >>>> 1. Chip has an original issue, need reset "WLAN" three times to avoid > >>>> it when power up. > >>>> > >>> 26 /* These three wlan reset will avoid original issue, > >>> 27 so full chip reset isn't needed here. */ > >>> 28 set_reg(0xb806001c, 0x00c06b30) > >>> 29 nop > >>> 30 set_reg(0xb806001c, 0x00c06330) > >>> 31 nop > >>> 32 set_reg(0xb806001c, 0x00c06b30) > >>> 33 nop > >>> 34 set_reg(0xb806001c, 0x00c06330) > >>> 35 nop > >>> 36 reset_wlan: > >>> 37 set_reg(0xb806001c, 0x00c06b30) > >>> 38 nop > >>> 39 set_reg(0xb806001c, 0x00c06330) > >>> 40 nop > >>> > >>> Yes, these can be done from C code. > >>> > >>>> 2. Need reset RTC and force to wake MAC, or chip can't work . > >>>> > >>> 73 /* RTC reset */ > >>> 74 set_reg(0x1810704c, 0x00000003) > >>> 75 nop > >>> 76 nop > >>> 77 set_reg(0x18107040, 0x00000000) > >>> 78 nop > >>> 79 nop > >>> 80 set_reg(0x18107040, 0x00000001) > >>> 81 nop > >>> > >>> DTTO. > >>> > >>>> 3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is > >>>> 25MHz, the interval from > >>>> power-up to printout is about 5s. > >>> > >>> The PLL configuration is again a set of writes to some random > >>> registers. This can again be done from the C code. > >>> > >>>> So, assembler code could not be avoided even using SRAM for c stack. > >>> > >>> I am not convinced, see above. Please show me where exactly is the > >>> assembly code imperative. I simply do not see it. > >>> > >>>> Now that chipmaker don't open SRAM of this chip and recommend DDR for > >>>> initial stack, i think > >>>> that using DDR should be more consolidated. > >>> > >>> I do not care what the chip maker says unless there is an explicit > >>> explanation why they require that. Most often, these sorts of > >>> "limitations" are in place only because the chipmaker has incompetent > >>> software engineers. > >>> > >>> So I would like to see either the SRAM or locked cacheline used for > >>> stack and then lowlevel init converted into proper C code unless there > >>> is an explicit explanation why this can not be done. And by explicit I > >>> mean for example a snippet of code which cannot be converted into C > >>> code. Note that asm volatile can still be used to contain such small > >>> bits of assembler code if needed be. > >>> > >>> Best regards, > >>> Marek Vasut > >> > >> I made a series of tries in this, i configure initial stack in SRAM and > >> convert > >> these code to c, and put them in arch_cpu_init(the first available c > >> entry), but > >> hardware don't work. if i keep the above three points(RESET/RTC/PLL) in > >> lowlevel_init, put other code in arch_cpu_init, board work fine. > > > > So let me ask the question again -- why does the C code not work ? Did > > you investigate the reason why does the C code not work ? > > > > Can you share the change you did to convert things to C code ? There > > might be a bug in that too ... > > it is not a matter of C or assembly, but of the init sequence currently > implemented on MIPS. The main purpose of lowlevel_init() is to > initialize memory controllers and DRAM. This has to be done in assembly > because we have no C runtime environment available at that point. We do this in C on ARM, so I see no problem with this. > Also compiling U-Boot as PIC requires to enable MIPS ABI function calls > in gcc (-mabicalls). This always creates function prologues and > epilogues which are utilizing the stack pointer. Thus we cannot simply > convert all lowlevel_init functions to C. I am not saying all, but a list of register writes should be easy to convert. > Moving code from lowlevel_init to arch_cpu_init or elsewhere will not > work because that code runs too late then. Simply moving the stack to > SRAM will also not help because lowlevel_init runs before the stack is > available. We have SRAM to place stack in, so stack is available. > Before Wills can convert his code to C, we need to rework the init > sequence in start.S. But that is out of the scope of this patch series. > I will try to prepare some patches in the next days. The SRAM part > should be easy. But the cache line lock need some more work and testing. > > In the meantime Wills could send a new patch series, which addresses all > other issues except lowlevel_init. The function ddr_tap_init can be > already converted to C because it is called from init_dram where a C > runtime environment is available. So we could have at least a working > patch series and could finalize the review of the other patches. After I > have updated u-boot-mips/next branch, Wills can rebase and convert > lowlevel_init to C.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6a9f798..da5fa72 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_ARCH_ATH79) += ath79 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 3ebc202..fd50909 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc PLATFORM_CPPFLAGS += $(cpuflags-y) PLATFORM_CPPFLAGS += -D__MIPS__ diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..bc0a41f --- /dev/null +++ b/arch/mips/mach-ath79/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/ diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile new file mode 100644 index 0000000..0da8fd4 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/Makefile @@ -0,0 +1,6 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += ddr_tap.o diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define DRAM_K0(x) KSEG0ADDR(x) +#define DRAM_K1(x) KSEG1ADDR(x) + + .text + .set noreorder + +LEAF(ddr_tap_init) + /* Tap settings for the DDR */ + li t0, 0xffffffff + li t1, DRAM_K0(0x500000) + sw t0, 0x0(t1) + sw t0, 0x4(t1) + sw t0, 0x8(t1) + sw t0, 0xc(t1) + nop + nop + + li t8, DRAM_K1(0x2000) + li t0, 0x00 + li t1, 0x100 +0: + andi t2, t0, 0x03 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x01 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x02 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x03 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x0(t8) +2: + andi t2, t0, 0x0c + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x04 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x08 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x0c + bne t2, t3,2f + li t9, 0xffffffff + sw t9, 0x4(t8) +2: + andi t2, t0, 0x30 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x10 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x20 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x30 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x8(t8) +2: + andi t2, t0, 0xc0 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x40 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x80 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0xc0 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0xc(t8) +2: + addiu t0, t0, 0x1 + addiu t8, t8, 0x10 + bne t0, t1, 0b + nop + + li a0, DRAM_K1(0x2000) # Start address + li a1, DRAM_K0(0x2000) # Start address of the pattern 200 + li a2, DRAM_K0(0x3000) # End Address of the pattern 220 + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + lw a3, AR71XX_DDR_REG_TAP_CTRL0(t0) + nop # loading default tap value + ori t0, a3, 0x0 + + /* $t1=1 indicates increasing tap value, 0 = decreasing */ + li t1, 0x1 +0: + li t7, 0x2 + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t0, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t0, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + /* t0 stores current tap setting under test + t1 indicates increment or decrement of tap */ +1: + ori t2, a0, 0x0 + ori t3, a1, 0x0 + ori t4, a2, 0x0 +2: + lw t5, 0x0(t2) # upper and lower limit detection + lw t6, 0x0(t3) + bne t5, t6, 3f + nop + addiu t2, t2, 0x4 + addiu t3, t3, 0x4 + bne t3, t4, 2b + nop + addiu t7, t7, -1 + bnez t7, 1b + nop + + bnez t1, 2f # increment tap if t1 = 1 + nop + bnez t0, 1f # tap=0 works so low limit=0, + nop # else decrement tap value + + li t8, DRAM_K0(0x500000) # assigning lower limit = 0 + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit to upper limit + b 4f # used to calc mid value + nop +1: + addiu t0, t0 , -1 # decrement and loading this new tap + b 0b + nop +2: + addiu t0, t0, 0x1 + xori v1, t0, 0x20 # limiting upper limit to 0x20 + bnez v1, 0b + nop + b 1f + nop +3: + bnez t1, 1f # t1=1 fail for upper limit + nop # t1=0 fail for lower limit + addiu t0, t0, 0x1 + nop + li t8, DRAM_K0(0x500000) # storing lower limit + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit and upper limit + b 4f + nop +1: + addiu t0, t0, -1 + li t1, 0x0 # changing to decreasing tap mode + li t8, DRAM_K0(0x500000) # storing upper limit + sw t0, 0x4(t8) + nop + ori t9, t0, 0x0 + ori t0, a3, 0x0 # loading default tap value + b 0b + nop + + /* calculating mid value of the tap, storing DQS0, DQS1 in + 0x80500008, 0x8050000c resp */ +4: + li t7, 0x2 + div t9, t7 + nop + mfhi t6 + mflo t5 + add t6, t6, t5 + li t8, DRAM_K0(0x500000) + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t5, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t6, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + nop + jr ra + nop + END(ddr_tap_init) diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2) + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +/* + * PLL_CPU_CONFIG_VAL + * + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) + * => 32 (0x20) VCOOUT = XTAL * DIV_INT + * bits 16..20 (5bit) REFDIV (Reference clock divider) + * => 1 (0x1) [Must start at values 1] + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) + * => 0 (0x0) [Doesn't impact clock values] + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) + * => 1 (0x1) [0 is illegal!] + * PLLOUT = VCOOUT * (1/2^OUTDIV) + */ +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) + +/* + * PLL_CLK_CONTROL_VAL + * + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. + * Software must enable the CPU PLL for normal and + * then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * CPU_CLK = PLLOUT / CPU_POST_DIV + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * DDR_CLK = PLLOUT / DDR_POST_DIV + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * AHB_CLK = PLLOUT / AHB_POST_DIV + * + */ +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) + + .text + .set noreorder + +LEAF(lowlevel_init) + /* These three WLAN_RESET will avoid original issue */ + li t3, 0x03 +1: + li t0, KSEG1ADDR(AR71XX_RESET_BASE) + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + ori t1, t1, 0x0800 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + li t2, 0xfffff7ff + and t1, t1, t2 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + addi t3, t3, -1 + bnez t3, 1b + nop + + li t2, 0x20 +2: + beqz t2, 1b + nop + addi t2, t2, -1 + lw t5, AR933X_RESET_REG_BOOTSTRAP(t0) + andi t1, t5, 0x10 + bnez t1, 2b + nop + + li t1, 0x02110E + sw t1, AR933X_RESET_REG_BOOTSTRAP(t0) + nop + + /* RTC Force Wake */ + li t0, KSEG1ADDR(AR933X_RTC_BASE) + li t1, 0x03 + sw t1, AR933X_RTC_REG_FORCE_WAKE(t0) + nop + nop + + /* RTC Reset */ + li t1, 0x00 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + li t1, 0x01 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + /* Wait for RTC in on state */ +1: + lw t1, AR933X_RTC_REG_STATUS(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + /* Program ki/kd */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x19e82f01 + b 2f + nop +1: + li t1, 0x18e82f01 +2: + sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0) + + /* Program phase shift */ + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xc07fffff + and t1, t1, t2 + li t2, 0x800000 # meas_at_txon + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Max AHB Master wait time out ... */ + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0xfffff + sw t1, AR933X_DDR_REG_TIMEOUT_MAX(t0) + nop + + /* in some cases, the SoC doesn't start with higher clock on AHB */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + /* Set SETTLE_TIME in CPU PLL */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x0352 + b 2f + nop +1: + li t1, 0x0550 +2: + sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0) + nop + + /* Set nint, frac, refdiv, outdiv, range according to xtal */ +0: + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) + b 2f + nop +1: + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Put frac bit19:10 configuration */ + li t1, 0x1003E8 + sw t1, AR71XX_PLL_REG_ETH0_INT_CLOCK(t0) + nop + + /* Clear PLL power down bit in CPU PLL configuration */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, PLL_CPU_CONFIG_VAL_25M + b 2f + nop +1: + li t1, PLL_CPU_CONFIG_VAL_40M +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop + + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Confirm DDR PLL lock */ + li t3, 100 + li t4, 0 + +2: + addi t4, t4, 1 + bgt t4, t3, 0b + nop + + li t3, 5 +3: + /* Clear do_meas */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xBFFFFFFF + and t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + li t2, 10 +1: + subu t2, t2, 1 + bnez t2, 1b + nop + + /* Set do_meas */ + li t2, 0x40000000 + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Check meas_done */ +1: + lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0) + andi t1, t1, 0x8 + beqz t1, 1b + nop + + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0x007FFFF8 + and t1, t1, t2 + srl t1, t1, 3 + li t2, 0x4000 + bgt t1, t2, 2b + nop + addi t3, t3, -1 + bnez t3, 3b + nop + + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, PLL_CLK_CONTROL_VAL + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0x7fbc8cd0 + sw t1, AR71XX_DDR_REG_CONFIG(t0) + + li t1, 0x9dd0e6a8 + sw t1, AR71XX_DDR_REG_CONFIG2(t0) + + andi t1, t5, 0x2000 # t5 BOOT_STRAP + beqz t1, 3f + nop + + /* Enable DDR2 */ + li t1, 0xA59 + sw t1, AR933X_DDR_REG_DDR2_CONFIG(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Disable High Temperature Self-Refresh Rate */ + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR2(t0) + + /* Extended Mode Register 2 Set (EMR2S) */ + li t1, 0x10 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR3(t0) + + /* Extended Mode Register 3 Set (EMR3S) */ + li t1, 0x20 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL */ + li t1, 0x00 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Reset DLL */ + li t1, 0x100 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + li t1, 0xa33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, + Reduced Drive Strength */ + li t1, 0x382 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 0(OCD exit), Enable DLL, + Reduced Drive Strength */ + li t1, 0x402 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4186 + b 2f + nop +1: + li t1, 0x4270 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + nop + b 4f + nop + + /* DDR1 config */ +3: + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write Mode Word */ + li t1, 0x133 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Forces an MRS update cycle in DDR */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL, High drive strength from DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Write Extended Mode Word of DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* DLL out of reset, CAS Latency 3 */ + li t1, 0x33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Write mode word */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4270 + b 2f + nop +1: + li t1, 0x4186 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + +4: + nop + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..1f58877 --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum ath79_soc_type get_soc_type(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + u32 id, major, minor; + + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + break; + + case REV_ID_MAJOR_QCA9533_V2: + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + break; + default: + break; + } + + return soc; +} + +int print_cpuinfo(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + char *chip = "????"; + u32 id, major, minor; + u32 rev = 0; + u32 ver = 1; + + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + chip = "9556"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + chip = "9558"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + chip = "9561"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + } + + puts("SoC: "); + switch (soc) { + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, ver, rev); + break; + case ATH79_SOC_TP9343: + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); + break; + case ATH79_SOC_UNKNOWN: + printf("ATH79: unknown SoC, id:0x%08x", id); + default: + printf("Atheros AR%s rev %u\n", chip, rev); + } + + return 0; +} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..42539dc --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/addrspace.h> +#include <asm/arch/ddr.h> + +phys_size_t initdram(int board_type) +{ + uint8_t *addr, *p; + int i; + + ddr_tap_init(); + addr = (uint8_t *)KSEG1; + *addr = 0x77; + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { + p += 0x1000000; + *p = i; + if (*addr != 0x77) + break; + } + return (phys_size_t)(p - addr); +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..228ae02 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -0,0 +1,1144 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang@live.com> + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define QCA953X_REV_ID_REVISION_MASK 0xf + +#define QCA955X_REV_ID_REVISION_MASK 0xf + +#define QCA956X_REV_ID_REVISION_MASK 0xf + +/* + * RTC block + */ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* + * SRIF block + */ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA955X_GPIO_OUT_GPIO 0 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* + * QCA953X GMAC Interface + */ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ diff --git a/arch/mips/mach-ath79/include/mach/ar933x_uart.h b/arch/mips/mach-ath79/include/mach/ar933x_uart.h new file mode 100644 index 0000000..40da419 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar933x_uart.h @@ -0,0 +1,66 @@ +/* + * Atheros AR933X UART defines + * + * Copyright (C) 2015 Wills Wang, <wills.wang@live.com> + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AR933X_UART_H +#define __AR933X_UART_H + +#define AR933X_UART_REGS_SIZE 20 +#define AR933X_UART_FIFO_SIZE 16 + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLOCK_REG 0x08 +#define AR933X_UART_INT_REG 0x0c +#define AR933X_UART_INT_EN_REG 0x10 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) + +#define AR933X_UART_CS_PARITY_S 0 +#define AR933X_UART_CS_PARITY_M 0x3 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_FLOW_CTRL_S 4 +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 +#define AR933X_UART_CS_DMA_EN BIT(6) +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) +#define AR933X_UART_CS_TX_READY BIT(9) +#define AR933X_UART_CS_RX_BREAK BIT(10) +#define AR933X_UART_CS_TX_BREAK BIT(11) +#define AR933X_UART_CS_HOST_INT BIT(12) +#define AR933X_UART_CS_HOST_INT_EN BIT(13) +#define AR933X_UART_CS_TX_BUSY BIT(14) +#define AR933X_UART_CS_RX_BUSY BIT(15) + +#define AR933X_UART_CLOCK_STEP_M 0xffff +#define AR933X_UART_CLOCK_SCALE_M 0xfff +#define AR933X_UART_CLOCK_SCALE_S 16 +#define AR933X_UART_CLOCK_STEP_S 0 + +#define AR933X_UART_INT_RX_VALID BIT(0) +#define AR933X_UART_INT_TX_READY BIT(1) +#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) +#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) +#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) +#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) +#define AR933X_UART_INT_RX_BREAK_ON BIT(6) +#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) +#define AR933X_UART_INT_RX_FULL BIT(8) +#define AR933X_UART_INT_TX_EMPTY BIT(9) +#define AR933X_UART_INT_ALLINTS 0x3ff + +#endif /* __AR933X_UART_H */ diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h new file mode 100644 index 0000000..15bb590 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -0,0 +1,143 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang@live.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA9561, +}; + +enum ath79_soc_type get_soc_type(void); + +static inline int soc_is_ar71xx(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7130 || + soc == ATH79_SOC_AR7141 || + soc == ATH79_SOC_AR7161; +} + +static inline int soc_is_ar724x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240 || + soc == ATH79_SOC_AR7241 || + soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar7240(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240; +} + +static inline int soc_is_ar7241(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7241; +} + +static inline int soc_is_ar7242(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar913x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9130 || + soc == ATH79_SOC_AR9132; +} + +static inline int soc_is_ar933x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9330 || + soc == ATH79_SOC_AR9331; +} + +static inline int soc_is_ar9341(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9341; +} + +static inline int soc_is_ar9342(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9342; +} + +static inline int soc_is_ar9344(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9344; +} + +static inline int soc_is_ar934x(enum ath79_soc_type soc) +{ + return soc_is_ar9341(soc) || + soc_is_ar9342(soc) || + soc_is_ar9344(soc); +} + +static inline int soc_is_qca9533(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(enum ath79_soc_type soc) +{ + return soc_is_qca9533(soc); +} + +static inline int soc_is_qca9556(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(enum ath79_soc_type soc) +{ + return soc_is_qca9556(soc) || soc_is_qca9558(soc); +} + +static inline int soc_is_tp9343(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9561; +} + +static inline int soc_is_qca956x(enum ath79_soc_type soc) +{ + return soc_is_tp9343(soc) || soc_is_qca9561(soc); +} + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h new file mode 100644 index 0000000..e90c9a1 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ddr.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_tap_init(void); + +#endif /* __ASM_MACH_DDR_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..0ace05d --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) + +DECLARE_GLOBAL_DATA_PTR; + +void _machine_restart(void) +{ + enum ath79_soc_type soc; + u32 val, reg = 0; + + soc = get_soc_type(); + if (soc_is_ar71xx(soc)) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x(soc)) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x(soc)) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x(soc)) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x(soc)) + reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x(soc)) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x(soc)) + reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x(soc)) + reg = QCA956X_RESET_REG_RESET_MODULE; + else + puts("Reset register not defined for this SOC\n"); + + if (reg) { + val = RST_READ(reg); + val |= AR71XX_RESET_FULL_CHIP; + RST_WRITE(reg, val); + } + + while (1) + /* NOP */; +}
This patch enable work for ar933x SOC, tested on ar9331 board. Signed-off-by: Wills Wang <wills.wang@live.com> --- Changes in v3: None Changes in v2: None arch/mips/Makefile | 1 + arch/mips/config.mk | 1 + arch/mips/mach-ath79/Makefile | 9 + arch/mips/mach-ath79/ar933x/Makefile | 6 + arch/mips/mach-ath79/ar933x/ddr_tap.S | 268 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 460 +++++++++ arch/mips/mach-ath79/cpu.c | 269 ++++++ arch/mips/mach-ath79/dram.c | 27 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1144 +++++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ar933x_uart.h | 66 ++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/reset.c | 55 ++ 13 files changed, 2462 insertions(+) create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ar933x_uart.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/reset.c