From patchwork Wed Jun 16 15:18:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: e500v2 36 bit large physical HID0[EN_MAS7_UPDATE] Date: Wed, 16 Jun 2010 05:18:36 -0000 From: Micha Nelissen X-Patchwork-Id: 55896 Message-Id: <4C18EB4C.4060201@neli.hopto.org> To: Kumar Gala Cc: linuxppc-dev@lists.ozlabs.org Micha Nelissen wrote: > Do you mean like attached? I had to change the order of the '_GLOBAL' > definitions __setup_cpu_e500v1/__setup_cpu_e500v2 since this bit is > e500v2 only. Hmm, maybe need to use r0 or r3 instead of r2? Micha Index: linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S =================================================================== --- linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S (revision 2871) +++ linux/arch/powerpc/kernel/cpu_setup_fsl_booke.S (working copy) @@ -57,8 +57,14 @@ ori r3,r3,HID0_DAPUEN@l mtspr SPRN_HID0,r3 b __setup_e200_ivors +_GLOBAL(__setup_cpu_e500v2) +#ifdef CONFIG_PTE_64BIT + /* enable mas7 register for tlbre/tlbsx */ + mfspr r0,SPRN_HID0 + ori r0,r0,HID0_EN_MAS7_UPDATE@l + mtspr SPRN_HID0,r0 +#endif _GLOBAL(__setup_cpu_e500v1) -_GLOBAL(__setup_cpu_e500v2) mflr r4 bl __e500_icache_setup bl __e500_dcache_setup Index: linux/arch/powerpc/include/asm/reg.h =================================================================== --- linux/arch/powerpc/include/asm/reg.h (revision 2871) +++ linux/arch/powerpc/include/asm/reg.h (working copy) @@ -276,6 +276,7 @@ #define HID0_DAPUEN (1<<8) /* Debug APU enable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ +#define HID0_EN_MAS7_UPDATE (1<<7) /* Enable MAS7 reg for tlbre/tlbsx */ #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */