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[U-Boot] arm: ls1021a: Adjust sata register default values

Message ID 1450245057-36524-1-git-send-email-Yuantian.Tang@freescale.com
State Accepted
Commit 1ef7ac70e24c40553307d5246cfa6ebd7394f2f1
Delegated to: York Sun
Headers show

Commit Message

tang yuantian Dec. 16, 2015, 5:50 a.m. UTC 
From: Tang Yuantian <Yuantian.Tang@freescale.com>

Updated the default sata register values to enhance the
performance and stability.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

York Sun Jan. 27, 2016, 4:45 p.m. UTC | #1 
On 12/15/2015 09:58 PM, Yuantian.Tang@freescale.com wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
> 
> Updated the default sata register values to enhance the
> performance and stability.
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
>  arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 

Applied to u-boot-fsl-qoriq master. Awaiting upstream.

Thanks.

York
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Patch

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
index deeb674..144f2c3 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -11,11 +11,11 @@ 
 
 /* port register default value */
 #define AHCI_PORT_PHY_1_CFG	0xa003fffe
-#define AHCI_PORT_PHY_2_CFG	0x28183411
-#define AHCI_PORT_PHY_3_CFG	0x0e081004
-#define AHCI_PORT_PHY_4_CFG	0x00480811
-#define AHCI_PORT_PHY_5_CFG	0x192c96a4
-#define AHCI_PORT_TRANS_CFG	0x08000025
+#define AHCI_PORT_PHY_2_CFG	0x28183414
+#define AHCI_PORT_PHY_3_CFG	0x0e080e06
+#define AHCI_PORT_PHY_4_CFG	0x064a080b
+#define AHCI_PORT_PHY_5_CFG	0x2aa86470
+#define AHCI_PORT_TRANS_CFG	0x08000029
 
 #define SATA_ECC_REG_ADDR	0x20220520
 #define SATA_ECC_DISABLE	0x00020000