diff mbox

Fix for MIPS PR target/65604

Message ID 1450213757.4788.125.camel@ubuntu-sellcey
State New
Headers show

Commit Message

Steve Ellcey Dec. 15, 2015, 9:09 p.m. UTC 
On Tue, 2015-12-15 at 15:13 +0000, Moore, Catherine wrote:

> 
> HI Steve, The patch is OK.  Will you please add a test case and repost?
> Thanks,
> Catherine

Here is the patch with a test case.

2015-12-15  Steve Ellcey  <sellcey@imgtec.com>

	PR target/65604
	* config/mips/mips.c (mips_output_division): Check flag_delayed_branch.

Comments

Moore, Catherine Dec. 16, 2015, 4:46 p.m. UTC | #1 
> -----Original Message-----
> From: Steve Ellcey [mailto:sellcey@imgtec.com]
> Sent: Tuesday, December 15, 2015 4:09 PM
> To: Moore, Catherine
> Cc: gcc-patches@gcc.gnu.org; matthew.fortune@imgtec.com
> Subject: RE: [Patch] Fix for MIPS PR target/65604
> 
> On Tue, 2015-12-15 at 15:13 +0000, Moore, Catherine wrote:
> 
> >
> > HI Steve, The patch is OK.  Will you please add a test case and repost?
> > Thanks,
> > Catherine
> 
> Here is the patch with a test case.
> 

Looks good, thanks.
diff mbox

Patch

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 6145944..8444a91 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13687,9 +13687,17 @@  mips_output_division (const char *division, rtx *operands)
 	}
       else
 	{
-	  output_asm_insn ("%(bne\t%2,%.,1f", operands);
-	  output_asm_insn (s, operands);
-	  s = "break\t7%)\n1:";
+	  if (flag_delayed_branch)
+	    {
+	      output_asm_insn ("%(bne\t%2,%.,1f", operands);
+	      output_asm_insn (s, operands);
+	      s = "break\t7%)\n1:";
+	    }
+	  else
+	    {
+	      output_asm_insn (s, operands);
+	      s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
+	    }
 	}
     }
   return s;



2015-12-15  Steve Ellcey  <sellcey@imgtec.com>

	PR target/65604
	* gcc.target/mips/div-delay.c: New test.


diff --git a/gcc/testsuite/gcc.target/mips/div-delay.c b/gcc/testsuite/gcc.target/mips/div-delay.c
index e69de29..bdeb125 100644
--- a/gcc/testsuite/gcc.target/mips/div-delay.c
+++ b/gcc/testsuite/gcc.target/mips/div-delay.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=mips1 -fno-delayed-branch" } */
+/* { dg-final { scan-assembler "\tbne\t.*\tnop" } } */
+
+/* Ensure that mips1 does not put anything in the delay slot of the bne
+   instruction when checking for divide by zero.  mips2+ systems use teq
+   instead of bne and teq has no delay slot.  */
+
+NOCOMPRESSION int
+foo (int a, int b)
+{
+  return a / b;
+}