diff mbox

[U-Boot,02/10] x86: ivybridge: Add FSP support

Message ID 1449831353-933-3-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Bin Meng
Headers show

Commit Message

Bin Meng Dec. 11, 2015, 10:55 a.m. UTC 
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
 arch/x86/cpu/ivybridge/Makefile                    |  4 ++
 arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
 arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
 .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
 6 files changed, 131 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
 create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h

Comments

Simon Glass Dec. 19, 2015, 2:52 a.m. UTC | #1 
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> IvyBridge FSP package is built with a base address at 0xfff80000,
> and does not use UPD data region. This adds basic FSP support.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>  6 files changed, 131 insertions(+)
>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

One question: why do we need an Intel license on this code?

- Simon
Bin Meng Dec. 21, 2015, 2:27 a.m. UTC | #2 
Hi Simon,

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> IvyBridge FSP package is built with a base address at 0xfff80000,
>> and does not use UPD data region. This adds basic FSP support.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>  6 files changed, 131 insertions(+)
>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> One question: why do we need an Intel license on this code?
>

It was a copy and paste from other platform (queensbay and baytrail)
files. Do you think we should change it to GPLv2+?

Regards,
Bin
Simon Glass Dec. 23, 2015, 4:44 p.m. UTC | #3 
Hi Bin,

On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>> and does not use UPD data region. This adds basic FSP support.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>>  6 files changed, 131 insertions(+)
>>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> Tested on link (ivybridge non-FSP)
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>> One question: why do we need an Intel license on this code?
>>
>
> It was a copy and paste from other platform (queensbay and baytrail)
> files. Do you think we should change it to GPLv2+?

Hmm - is it using this license because it was written by Intel, or
because you modified it from the FSP code that was written by Intel?
If so, then I suppose it is reasonable to use the Intel license.

Regards,
Simon
Bin Meng Dec. 23, 2015, 10:48 p.m. UTC | #4 
Hi Simon,

On Thu, Dec 24, 2015 at 12:44 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>>> and does not use UPD data region. This adds basic FSP support.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>>>  6 files changed, 131 insertions(+)
>>>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> Tested on link (ivybridge non-FSP)
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>
>>> One question: why do we need an Intel license on this code?
>>>
>>
>> It was a copy and paste from other platform (queensbay and baytrail)
>> files. Do you think we should change it to GPLv2+?
>
> Hmm - is it using this license because it was written by Intel, or
> because you modified it from the FSP code that was written by Intel?
> If so, then I suppose it is reasonable to use the Intel license.
>

The file was not written by Intel. Current U-Boot implementation is
our own. I will change the license in v2.

Regards,
Bin
diff mbox

Patch

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 56abd8f..36b74c2 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -72,4 +72,12 @@  config ENABLE_VMX
 	  will be unable to support virtualisation, or it will run very
 	  slowly.
 
+config FSP_ADDR
+	hex
+	default 0xfff80000
+
+config FSP_USE_UPD
+	bool
+	default n
+
 endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 0c7efae..d74635e 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -4,6 +4,9 @@ 
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifdef CONFIG_HAVE_FSP
+obj-y += fsp_configs.o ivybridge.o
+else
 obj-y += bd82x6x.o
 obj-y += car.o
 obj-y += cpu.o
@@ -22,3 +25,4 @@  obj-y += sata.o
 obj-y += sdram.o
 obj-y += usb_ehci.o
 obj-y += usb_xhci.o
+endif
diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c
new file mode 100644
index 0000000..5d8b814
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/fsp_configs.c
@@ -0,0 +1,45 @@ 
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void update_fsp_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
+{
+	struct platform_config *plat_config = &config->plat_config;
+	struct memory_config *mem_config = &config->mem_config;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP);
+	if (node < 0) {
+		debug("%s: Cannot find FSP node\n", __func__);
+		return;
+	}
+
+	plat_config->enable_ht =
+		fdtdec_get_bool(blob, node, "fsp,enable-ht");
+	plat_config->enable_turbo =
+		fdtdec_get_bool(blob, node, "fsp,enable-turbo");
+	plat_config->enable_memory_down =
+		fdtdec_get_bool(blob, node, "fsp,enable-memory-down");
+	plat_config->enable_fast_boot =
+		fdtdec_get_bool(blob, node, "fsp,enable-fast-boot");
+
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->stack_top = config->common.stack_top - 32;
+	rt_buf->boot_mode = config->common.boot_mode;
+	rt_buf->plat_config = plat_config;
+
+	if (plat_config->enable_memory_down)
+		rt_buf->mem_config = mem_config;
+	else
+		rt_buf->mem_config = NULL;
+}
diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c
new file mode 100644
index 0000000..afe7e57
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/ivybridge.c
@@ -0,0 +1,22 @@ 
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	post_code(POST_CPU_INIT);
+
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
new file mode 100644
index 0000000..24e2f2f
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
@@ -0,0 +1,40 @@ 
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct platform_config {
+	u8 enable_ht;
+	u8 enable_turbo;
+	u8 enable_memory_down;
+	u8 enable_fast_boot;
+};
+
+/*
+ * Dummy structure for now as currently only SPD is verified in U-Boot.
+ *
+ * We can add the missing parameters when adding support on a board with
+ * memory down configuration.
+ */
+struct memory_config {
+	u8 dummy;
+};
+
+struct fsp_config_data {
+	struct fsp_cfg_common common;
+	struct platform_config plat_config;
+	struct memory_config mem_config;
+};
+
+struct fspinit_rtbuf {
+	u32 stack_top;
+	u32 boot_mode;
+	struct platform_config *plat_config;
+	struct memory_config *mem_config;
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
new file mode 100644
index 0000000..be9f055
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
@@ -0,0 +1,12 @@ 
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+/* IvyBridge FSP does not support VPD/UPD */
+
+#endif