| Message ID | 3bc15df0-329f-43ed-820a-5de264b5c7c3@BAMAIL02.ba.imgtec.org |
|---|---|
| State | New |
| Headers | show |
> -----Original Message----- > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches- > owner@gcc.gnu.org] On Behalf Of Steve Ellcey > Sent: Wednesday, December 09, 2015 1:34 PM > To: gcc-patches@gcc.gnu.org > Cc: Moore, Catherine; matthew.fortune@imgtec.com > Subject: [Patch] Fix for MIPS PR target/65604 > > This is a MIPS patch to make mips_output_division obey the -fno-delayed- > branch flag. Right now, with mips1 and -mcheck-zero-division, the division > instruction is put into the bne delay slot even when -fno-delayed-branch is > specified. This change uses a similar strategy to MIPS16 where we do the > division first and then do the zero test while the division is being calculated. > Tested with mips1 runs and by inspecting the code that is output. > > OK to checkin? > > Steve Ellcey > sellcey@imgtec.com > > > 2015-12-09 Steve Ellcey <sellcey@imgtec.com> > > PR target/65604 > * config/mips/mips.c (mips_output_division): Check > flag_delayed_branch. > HI Steve, The patch is OK. Will you please add a test case and repost? Thanks, Catherine
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 6145944..8444a91 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -13687,9 +13687,17 @@ mips_output_division (const char *division, rtx *operands) } else { - output_asm_insn ("%(bne\t%2,%.,1f", operands); - output_asm_insn (s, operands); - s = "break\t7%)\n1:"; + if (flag_delayed_branch) + { + output_asm_insn ("%(bne\t%2,%.,1f", operands); + output_asm_insn (s, operands); + s = "break\t7%)\n1:"; + } + else + { + output_asm_insn (s, operands); + s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:"; + } } } return s;