| Message ID | 1449545956-2772-8-git-send-email-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
Hi Simon, On Tue, Dec 8, 2015 at 11:38 AM, Simon Glass <sjg@chromium.org> wrote: > Move this code to the LPC's probe() method so that it will happen > automatically when the LPC is probed before relocation. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/cpu/ivybridge/cpu.c | 9 --------- > arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- > arch/x86/dts/chromebook_link.dts | 2 +- > arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- > 4 files changed, 26 insertions(+), 27 deletions(-) > > diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c > index fd7e1fc..73c9929 100644 > --- a/arch/x86/cpu/ivybridge/cpu.c > +++ b/arch/x86/cpu/ivybridge/cpu.c > @@ -124,10 +124,8 @@ int arch_cpu_init(void) > > int arch_cpu_init_dm(void) > { > - const void *blob = gd->fdt_blob; > struct pci_controller *hose; > struct udevice *bus, *dev; > - int node; > int ret; > > post_code(0x70); > @@ -145,13 +143,6 @@ int arch_cpu_init_dm(void) > if (!dev) > return -ENODEV; > > - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); > - if (node < 0) > - return -ENOENT; > - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); > - if (ret) > - return ret; > - > enable_spi_prefetch(hose, PCH_LPC_DEV); > > /* This is already done in start.S, but let's do it in C */ > diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c > index 04a7451..e6f25e1 100644 > --- a/arch/x86/cpu/ivybridge/lpc.c > +++ b/arch/x86/cpu/ivybridge/lpc.c > @@ -463,7 +463,13 @@ static void pch_fixups(pci_dev_t dev) > setbits_le32(RCB_REG(0x21a8), 0x3); > } > > -int lpc_early_init(const void *blob, int node, pci_dev_t dev) > +/** > + * lpc_early_init() - set up LPC serial ports and other early things > + * > + * @dev: LPC device > + * @return 0 if OK, -ve on error > + */ > +static int lpc_early_init(struct udevice *dev) > { > struct reg_info { > u32 base; > @@ -472,17 +478,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) > int count; > int i; > > - count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", > - (u32 *)values, sizeof(values) / sizeof(u32)); > + count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, > + "intel,gen-dec", (u32 *)values, > + sizeof(values) / sizeof(u32)); > if (count < 0) > return -EINVAL; > > /* Set COM1/COM2 decode range */ > - x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); > + dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010); This looks quite odd, as LPC (this device) driver is writing some register that resides in its parent's (dev->parent) register space. As I mentioned previously, I don't understand why we create this LPC uclass under PCH uclass. Physically they are actually the same device. > > /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ > - x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | > - GAMEL_LPC_EN | COMA_LPC_EN); > + dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | > + GAMEL_LPC_EN | COMA_LPC_EN); > > /* Write all registers but use 0 if we run out of data */ > count = count * sizeof(u32) / sizeof(values[0]); > @@ -491,7 +498,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) > > if (i < count) > reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); > - x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); > + dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); > } > > return 0; > @@ -570,6 +577,17 @@ void lpc_enable(pci_dev_t dev) > > static int bd82x6x_lpc_probe(struct udevice *dev) > { > + int ret; > + > + if (gd->flags & GD_FLG_RELOC) > + return 0; > + > + ret = lpc_early_init(dev); > + if (ret) { > + debug("%s: lpc_early_init() failed\n", __func__); > + return ret; > + } > + > return 0; > } > > diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts > index 7a009db..144442d 100644 > --- a/arch/x86/dts/chromebook_link.dts > +++ b/arch/x86/dts/chromebook_link.dts > @@ -193,7 +193,6 @@ > #address-cells = <1>; > #size-cells = <1>; > gen-dec = <0x800 0xfc 0x900 0xfc>; What is this? Looks the same as 'intel,gen-dec'. > - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; > intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b > 0x80 0x80 0x80 0x80>; > intel,gpi-routing = <0 0 0 0 0 0 0 2 > @@ -224,6 +223,7 @@ > #address-cells = <1>; > #size-cells = <0>; > u-boot,dm-pre-reloc; > + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; > cros-ec@200 { > compatible = "google,cros-ec"; > reg = <0x204 1 0x200 1 0x880 0x80>; > diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h > index 21df083..73309be 100644 > --- a/arch/x86/include/asm/arch-ivybridge/pch.h > +++ b/arch/x86/include/asm/arch-ivybridge/pch.h > @@ -463,14 +463,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); > int lpc_init(struct pci_controller *hose, pci_dev_t dev); > void lpc_enable(pci_dev_t dev); > > -/** > - * lpc_early_init() - set up LPC serial ports and other early things > - * > - * @blob: Device tree blob > - * @node: Offset of LPC node > - * @dev: PCH PCI device containing the LPC > - * @return 0 if OK, -ve on error > - */ > -int lpc_early_init(const void *blob, int node, pci_dev_t dev); > - > #endif > -- Regards, Bin
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index fd7e1fc..73c9929 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -124,10 +124,8 @@ int arch_cpu_init(void) int arch_cpu_init_dm(void) { - const void *blob = gd->fdt_blob; struct pci_controller *hose; struct udevice *bus, *dev; - int node; int ret; post_code(0x70); @@ -145,13 +143,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); - if (ret) - return ret; - enable_spi_prefetch(hose, PCH_LPC_DEV); /* This is already done in start.S, but let's do it in C */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 04a7451..e6f25e1 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -463,7 +463,13 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); } -int lpc_early_init(const void *blob, int node, pci_dev_t dev) +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @dev: LPC device + * @return 0 if OK, -ve on error + */ +static int lpc_early_init(struct udevice *dev) { struct reg_info { u32 base; @@ -472,17 +478,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) int count; int i; - count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", - (u32 *)values, sizeof(values) / sizeof(u32)); + count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, + "intel,gen-dec", (u32 *)values, + sizeof(values) / sizeof(u32)); if (count < 0) return -EINVAL; /* Set COM1/COM2 decode range */ - x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); + dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010); /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - GAMEL_LPC_EN | COMA_LPC_EN); + dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN); /* Write all registers but use 0 if we run out of data */ count = count * sizeof(u32) / sizeof(values[0]); @@ -491,7 +498,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) if (i < count) reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); - x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); + dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); } return 0; @@ -570,6 +577,17 @@ void lpc_enable(pci_dev_t dev) static int bd82x6x_lpc_probe(struct udevice *dev) { + int ret; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + ret = lpc_early_init(dev); + if (ret) { + debug("%s: lpc_early_init() failed\n", __func__); + return ret; + } + return 0; } diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7a009db..144442d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -193,7 +193,6 @@ #address-cells = <1>; #size-cells = <1>; gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 0x80 0x80 0x80 0x80>; intel,gpi-routing = <0 0 0 0 0 0 0 2 @@ -224,6 +223,7 @@ #address-cells = <1>; #size-cells = <0>; u-boot,dm-pre-reloc; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083..73309be 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -463,14 +463,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); int lpc_init(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev); -/** - * lpc_early_init() - set up LPC serial ports and other early things - * - * @blob: Device tree blob - * @node: Offset of LPC node - * @dev: PCH PCI device containing the LPC - * @return 0 if OK, -ve on error - */ -int lpc_early_init(const void *blob, int node, pci_dev_t dev); - #endif
Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 27 deletions(-)