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ARC: [axs10x] cap ethernet phy to 100 Mbit/sec

Message ID 1449487297-10093-1-git-send-email-abrodkin@synopsys.com
State Accepted, archived
Delegated to: Vineet Gupta
Headers show

Commit Message

Alexey Brodkin Dec. 7, 2015, 11:21 a.m. UTC
Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.

To make sure networking is stable on the board we're
limiting phy to 100 Mbit.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
---
 arch/arc/boot/dts/axs10x_mb.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Vineet Gupta Dec. 7, 2015, 2:09 p.m. UTC | #1
On Monday 07 December 2015 04:52 PM, Alexey Brodkin wrote:

Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.

To make sure networking is stable on the board we're
limiting phy to 100 Mbit.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com><mailto:abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com><mailto:vgupta@synopsys.com>

LGTM - added to for-curr for 4.4 !

Thx,
-Vineet
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Patch

diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index f3db321..44a578c 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -46,6 +46,7 @@ 
 			snps,pbl = < 32 >;
 			clocks = <&apbclk>;
 			clock-names = "stmmaceth";
+			max-speed = <100>;
 		};
 
 		ehci@0x40000 {