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[OpenWrt-Devel,v6,2/6] ar71xx: add rx/tx delay definitons for qca955x's MAC

Message ID fd3ad5c44c3c7d0a67376654e4e7bf0d5052e1ab.1449350080.git.chunkeey@googlemail.com
State Accepted
Headers show

Commit Message

Christian Lamparter Dec. 5, 2015, 10:48 p.m. UTC 
From: Chris R Blake <chrisrblake93@gmail.com>

This patch adds the rx/tx register offsets for the qca955x SoC.

Signed-off-by: Chris R Blake <chrisrblake93@gmail.com>
---
 .../742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch  | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
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Patch

diff --git a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
new file mode 100644
index 0000000..2d89fd8
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch
@@ -0,0 +1,14 @@ 
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1098,5 +1098,11 @@
+
+ #define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
+ #define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
++#define QCA955X_ETH_CFG_RXD_DELAY	BIT(14)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK	0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT	14
++#define QCA955X_ETH_CFG_RDV_DELAY	BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK	0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT	16
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */