Patchwork [ARM] Tweak CLASS_LIKELY_SPILLED_P, MODE_BASE_REG_CLASS for Thumb-2

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Submitter Julian Brown
Date June 10, 2010, 11:26 a.m.
Message ID <20100610122652.4dee6376@rex.config>
Download mbox | patch
Permalink /patch/55203/
State New
Headers show

Comments

Julian Brown - June 10, 2010, 11:26 a.m.
On Tue, 08 Jun 2010 09:44:53 +0100
Richard Earnshaw <rearnsha@arm.com> wrote:

> 
> On Mon, 2010-06-07 at 19:57 +0100, Julian Brown wrote:
> > On Fri, 28 May 2010 14:04:29 +0100
> > Richard Earnshaw <rearnsha@arm.com> wrote:
> > 
> > > 
> > > On Fri, 2010-05-28 at 12:26 +0100, Julian Brown wrote:
> > > >  /* The class value for index registers, and the one for base
> > > > regs. */
> > > > @@ -1260,7 +1263,7 @@ enum reg_class
> > > >     when addressing quantities in QI or HI mode; if we don't
> > > > know the mode, then we must be conservative.  */
> > > >  #define
> > > > MODE_BASE_REG_CLASS(MODE)                                      \
> > > > -    (TARGET_32BIT ?
> > > > CORE_REGS :                                        \
> > > > +    (TARGET_32BIT ? (TARGET_THUMB2 ? LO_REGS :
> > > > CORE_REGS) :                                    \
> > > >       (((MODE) == SImode) ? BASE_REGS : LO_REGS))
> > > >  
> > > 
> > > Why not change the first test to TARGET_ARM?
> > 
> > (I think you mean like the attached patch.)
> 
> ENOPATCH

D'oh, sorry. Here it is.

Julian
Richard Earnshaw - June 10, 2010, 3:31 p.m.
On Thu, 2010-06-10 at 12:26 +0100, Julian Brown wrote:
> On Tue, 08 Jun 2010 09:44:53 +0100
> Richard Earnshaw <rearnsha@arm.com> wrote:
> 
> > 
> > On Mon, 2010-06-07 at 19:57 +0100, Julian Brown wrote:
> > > On Fri, 28 May 2010 14:04:29 +0100
> > > Richard Earnshaw <rearnsha@arm.com> wrote:
> > > 
> > > > 
> > > > On Fri, 2010-05-28 at 12:26 +0100, Julian Brown wrote:
> > > > >  /* The class value for index registers, and the one for base
> > > > > regs. */
> > > > > @@ -1260,7 +1263,7 @@ enum reg_class
> > > > >     when addressing quantities in QI or HI mode; if we don't
> > > > > know the mode, then we must be conservative.  */
> > > > >  #define
> > > > > MODE_BASE_REG_CLASS(MODE)                                      \
> > > > > -    (TARGET_32BIT ?
> > > > > CORE_REGS :                                        \
> > > > > +    (TARGET_32BIT ? (TARGET_THUMB2 ? LO_REGS :
> > > > > CORE_REGS) :                                    \
> > > > >       (((MODE) == SImode) ? BASE_REGS : LO_REGS))
> > > > >  
> > > > 
> > > > Why not change the first test to TARGET_ARM?
> > > 
> > > (I think you mean like the attached patch.)
> > 
> > ENOPATCH
> 
> D'oh, sorry. Here it is.

Yes.  OK (modulo the noise from the changes in gcc/*.c)

R.
Julian Brown - June 15, 2010, 11:21 a.m.
On Thu, 10 Jun 2010 16:31:12 +0100
Richard Earnshaw <rearnsha@arm.com> wrote:

> Yes.  OK (modulo the noise from the changes in gcc/*.c)

Thanks. Ping (for target-independent changes)?

Julian

Patch

Index: gcc/regrename.c
===================================================================
--- gcc/regrename.c	(revision 159320)
+++ gcc/regrename.c	(working copy)
@@ -26,7 +26,6 @@ 
 #include "tm_p.h"
 #include "insn-config.h"
 #include "regs.h"
-#include "addresses.h"
 #include "hard-reg-set.h"
 #include "basic-block.h"
 #include "reload.h"
@@ -34,6 +33,7 @@ 
 #include "function.h"
 #include "recog.h"
 #include "flags.h"
+#include "addresses.h"
 #include "toplev.h"
 #include "obstack.h"
 #include "timevar.h"
Index: gcc/recog.c
===================================================================
--- gcc/recog.c	(revision 159320)
+++ gcc/recog.c	(working copy)
@@ -31,10 +31,10 @@  along with GCC; see the file COPYING3.  
 #include "hard-reg-set.h"
 #include "recog.h"
 #include "regs.h"
-#include "addresses.h"
 #include "expr.h"
 #include "function.h"
 #include "flags.h"
+#include "addresses.h"
 #include "real.h"
 #include "toplev.h"
 #include "basic-block.h"
Index: gcc/config/arm/arm.h
===================================================================
--- gcc/config/arm/arm.h	(revision 159320)
+++ gcc/config/arm/arm.h	(working copy)
@@ -1245,11 +1245,14 @@  enum reg_class
      || reg_classes_intersect_p (VFP_REGS, (CLASS))	\
    : 0)
 
-/* We need to define this for LO_REGS on thumb.  Otherwise we can end up
-   using r0-r4 for function arguments, r7 for the stack frame and don't
-   have enough left over to do doubleword arithmetic.  */
+/* We need to define this for LO_REGS on Thumb-1.  Otherwise we can end up
+   using r0-r4 for function arguments, r7 for the stack frame and don't have
+   enough left over to do doubleword arithmetic.  For Thumb-2 all the
+   potentially problematic instructions accept high registers so this is not
+   necessary.  Care needs to be taken to avoid adding new Thumb-2 patterns
+   that require many low registers.  */
 #define CLASS_LIKELY_SPILLED_P(CLASS)	\
-    ((TARGET_THUMB && (CLASS) == LO_REGS)	\
+    ((TARGET_THUMB1 && (CLASS) == LO_REGS)	\
      || (CLASS) == CC_REG)
 
 /* The class value for index registers, and the one for base regs.  */
@@ -1260,7 +1263,7 @@  enum reg_class
    when addressing quantities in QI or HI mode; if we don't know the
    mode, then we must be conservative.  */
 #define MODE_BASE_REG_CLASS(MODE)					\
-    (TARGET_32BIT ? CORE_REGS :					\
+    (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS :	\
      (((MODE) == SImode) ? BASE_REGS : LO_REGS))
 
 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
Index: gcc/regcprop.c
===================================================================
--- gcc/regcprop.c	(revision 159320)
+++ gcc/regcprop.c	(working copy)
@@ -26,7 +26,6 @@ 
 #include "tm_p.h"
 #include "insn-config.h"
 #include "regs.h"
-#include "addresses.h"
 #include "hard-reg-set.h"
 #include "basic-block.h"
 #include "reload.h"
@@ -34,6 +33,7 @@ 
 #include "function.h"
 #include "recog.h"
 #include "flags.h"
+#include "addresses.h"
 #include "toplev.h"
 #include "obstack.h"
 #include "timevar.h"