| Message ID | 565F81A6.6060307@simon.arlott.org.uk |
|---|---|
| State | Superseded |
| Headers | show |
On Wed, Dec 02, 2015 at 11:41:26PM +0000, Simon Arlott wrote: > Add device tree binding for NAND on the BCM6368. > > The BCM6368 has a NAND interrupt register with combined status and enable > registers. It also requires a clock, so add an optional clock to the > common brcmnand binding. > > Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Acked-by: Rob Herring <robh@kernel.org> > --- > Renamed from BCM63268, made clock a generic property. > > .../devicetree/bindings/mtd/brcm,brcmnand.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > index 4ff7128..16d7835 100644 > --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > @@ -45,6 +45,8 @@ Required properties: > - #size-cells : <0> > > Optional properties: > +- clock : reference to the clock for the NAND controller > +- clock-names : "nand" (required for the above clock) > - brcm,nand-has-wp : Some versions of this IP include a write-protect > (WP) control bit. It is always available on >= > v7.0. Use this property to describe the rare > @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w > and enable registers > - reg-names: (required) "nand-int-base" > > + * "brcm,nand-bcm6368" > + - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368" > + - reg: (required) the 'NAND_INTR_BASE' register range, with combined status > + and enable registers, and boot address registers > + - reg-names: (required) "nand-intr-base" > + > * "brcm,nand-iproc" > - reg: (required) the "IDM" register range, for interrupt enable and APB > bus access endianness configuration, and the "EXT" register range, > @@ -148,3 +156,27 @@ nand@f0442800 { > }; > }; > }; > + > +nand@10000200 { > + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", > + "brcm,brcmnand-v4.0", "brcm,brcmnand"; > + reg = <0x10000200 0x180>, > + <0x10000600 0x200>, > + <0x100000b0 0x10>; > + reg-names = "nand", "nand-cache", "nand-intr-base"; > + interrupt-parent = <&periph_intc>; > + interrupts = <50>; > + clocks = <&periph_clk 20>; > + clock-names = "nand"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + nand0: nandcs@0 { > + compatible = "brcm,nandcs"; > + reg = <0>; > + nand-on-flash-bbt; > + nand-ecc-strength = <1>; > + nand-ecc-step-size = <512>; > + }; > +}; > -- > 2.1.4 > > -- > Simon Arlott
On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote: > Add device tree binding for NAND on the BCM6368. > > The BCM6368 has a NAND interrupt register with combined status and enable > registers. It also requires a clock, so add an optional clock to the > common brcmnand binding. > > Signed-off-by: Simon Arlott <simon@fire.lp0.eu> > --- > Renamed from BCM63268, made clock a generic property. > > .../devicetree/bindings/mtd/brcm,brcmnand.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > index 4ff7128..16d7835 100644 > --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt > @@ -45,6 +45,8 @@ Required properties: > - #size-cells : <0> > > Optional properties: > +- clock : reference to the clock for the NAND controller > +- clock-names : "nand" (required for the above clock) > - brcm,nand-has-wp : Some versions of this IP include a write-protect > (WP) control bit. It is always available on >= > v7.0. Use this property to describe the rare > @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w > and enable registers > - reg-names: (required) "nand-int-base" > > + * "brcm,nand-bcm6368" > + - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368" > + - reg: (required) the 'NAND_INTR_BASE' register range, with combined status > + and enable registers, and boot address registers > + - reg-names: (required) "nand-intr-base" Can't we use the same name as bcm63138, i.e. nand-int-base? > + > * "brcm,nand-iproc" > - reg: (required) the "IDM" register range, for interrupt enable and APB > bus access endianness configuration, and the "EXT" register range, > @@ -148,3 +156,27 @@ nand@f0442800 { > }; > }; > }; > + > +nand@10000200 { > + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", > + "brcm,brcmnand-v4.0", "brcm,brcmnand"; I know it's now much too late, but this is IMHO a very odd way of defining that this is a v4 nand, but uses bcm6368 compatible interrupts, as bcm6368 is a much older, unsupported nand revision. Jonas
On Fri, December 4, 2015 16:04, Jonas Gorski wrote: > On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote: >> + * "brcm,nand-bcm6368" >> + - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368" >> + - reg: (required) the 'NAND_INTR_BASE' register range, with combined status >> + and enable registers, and boot address registers >> + - reg-names: (required) "nand-intr-base" > > Can't we use the same name as bcm63138, i.e. nand-int-base? Brian, Before I change this, is there anything else in the patch series that needs to be changed? (I'll keep the comment referring to "NAND_INTR_BASE" the same because that's the name in the original #define for this hardware.)
On Fri, Dec 04, 2015 at 09:29:55PM -0000, Simon Arlott wrote: > On Fri, December 4, 2015 16:04, Jonas Gorski wrote: > > On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote: > >> + * "brcm,nand-bcm6368" > >> + - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368" > >> + - reg: (required) the 'NAND_INTR_BASE' register range, with combined status > >> + and enable registers, and boot address registers > >> + - reg-names: (required) "nand-intr-base" > > > > Can't we use the same name as bcm63138, i.e. nand-int-base? > > Brian, > > Before I change this, is there anything else in the patch series that needs to > be changed? No, I think you covered my comments in your latest series: http://lists.infradead.org/pipermail/linux-mtd/2015-December/064004.html I don't know about Jonas's comments about using bcm6368, even though bcm6368 is a much older NAND core. I had similar thoughts when Florian first proposed it, but I'm not sure I have a much better suggestion. We're trying to describe two slightly different tracks of IP: the core NAND controller, which has a defined revision (2.x, 4.0, etc.), and the accessory interrupt bits, which are mostly constant across a product line / class of SoCs and aren't really versioned. So I guess I'm OK with the usage of the bcm6368 compatible string. Regards, Brian
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt index 4ff7128..16d7835 100644 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt @@ -45,6 +45,8 @@ Required properties: - #size-cells : <0> Optional properties: +- clock : reference to the clock for the NAND controller +- clock-names : "nand" (required for the above clock) - brcm,nand-has-wp : Some versions of this IP include a write-protect (WP) control bit. It is always available on >= v7.0. Use this property to describe the rare @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w and enable registers - reg-names: (required) "nand-int-base" + * "brcm,nand-bcm6368" + - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368" + - reg: (required) the 'NAND_INTR_BASE' register range, with combined status + and enable registers, and boot address registers + - reg-names: (required) "nand-intr-base" + * "brcm,nand-iproc" - reg: (required) the "IDM" register range, for interrupt enable and APB bus access endianness configuration, and the "EXT" register range, @@ -148,3 +156,27 @@ nand@f0442800 { }; }; }; + +nand@10000200 { + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", + "brcm,brcmnand-v4.0", "brcm,brcmnand"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + reg-names = "nand", "nand-cache", "nand-intr-base"; + interrupt-parent = <&periph_intc>; + interrupts = <50>; + clocks = <&periph_clk 20>; + clock-names = "nand"; + + #address-cells = <1>; + #size-cells = <0>; + + nand0: nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; + }; +};
Add device tree binding for NAND on the BCM6368. The BCM6368 has a NAND interrupt register with combined status and enable registers. It also requires a clock, so add an optional clock to the common brcmnand binding. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> --- Renamed from BCM63268, made clock a generic property. .../devicetree/bindings/mtd/brcm,brcmnand.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+)