pinctrl: sh-pfc: r8a7791: add EtherAVB pin groups
diff mbox

Message ID 1512650.VUqGxiAB2A@wasted.cogentembedded.com
State New
Headers show

Commit Message

Sergei Shtylyov Dec. 2, 2015, 8:11 p.m. UTC
Add the EtherAVB pin groups to the R8A7791 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
The patch is against the 'devel' branch of Linus W.'s 'linux-pinctrl.git' repo.

 drivers/pinctrl/sh-pfc/pfc-r8a7791.c |   92 +++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)


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Comments

Geert Uytterhoeven Dec. 8, 2015, 12:12 p.m. UTC | #1
Hi Sergei,

On Wed, Dec 2, 2015 at 9:11 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the EtherAVB pin groups to the R8A7791 PFC driver.

Thanks for your patch!

> +static const unsigned int avb_mii_pins[] = {
> +       RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
> +       RCAR_GP_PIN(5, 21),
> +
> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
> +       RCAR_GP_PIN(5, 3),
> +
> +       RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
> +       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 28),
> +       RCAR_GP_PIN(5, 29),
> +};
> +static const unsigned int avb_mii_mux[] = {
> +       AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +       AVB_TXD3_MARK,
> +
> +       AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +       AVB_RXD3_MARK,
> +
> +       AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +       AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
> +       AVB_COL_MARK,
> +};

The MII pin list include RX_ER, but not TX_ER...

> +static const unsigned int avb_gmii_pins[] = {
> +       RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
> +       RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
> +       RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
> +
> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
> +       RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
> +       RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
> +
> +       RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
> +       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
> +       RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
> +       RCAR_GP_PIN(5, 29),
> +};
> +static const unsigned int avb_gmii_mux[] = {
> +       AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +       AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
> +       AVB_TXD6_MARK, AVB_TXD7_MARK,
> +
> +       AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +       AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
> +       AVB_RXD6_MARK, AVB_RXD7_MARK,
> +
> +       AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +       AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
> +       AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
> +       AVB_COL_MARK,
> +};

... while the GMII pin list includes both RX_ER and TX_ER. Is that correct?
Should it be the other way around?

Section "45A.3.13.1 MII Frame Transmission/Reception Timing" of the R-Car Gen2
datasheet shows timing diagrams for both AVB_TX_ER and AVB_RX_ER, so I'd expect
both pins to be needed for MII.

Unfortunately Section "45A.3.13.2 GMII Frame Reception Timing" shows timing
diagrams for receive only (thus involving AVB_RX_ER only), so I'm not sure the
AVB_TX_ER pin is actually needed for GMII.

I don't have schematics for any R-Car Gen2 board that has AVB support, so I
can't check myself how the MII/GMII is really wired.

Note that this also applies to the existing AVB pinmux data in pfc-r8a7790.c.

Can you please check/clarify? I'm not an Ethernet PHY expert.

Thanks again!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Sergei Shtylyov Dec. 8, 2015, 12:30 p.m. UTC | #2
Hello.

On 12/8/2015 3:12 PM, Geert Uytterhoeven wrote:

>> Add the EtherAVB pin groups to the R8A7791 PFC driver.
>
> Thanks for your patch!
>
>> +static const unsigned int avb_mii_pins[] = {
>> +       RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
>> +       RCAR_GP_PIN(5, 21),
>> +
>> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
>> +       RCAR_GP_PIN(5, 3),
>> +
>> +       RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
>> +       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 28),
>> +       RCAR_GP_PIN(5, 29),
>> +};
>> +static const unsigned int avb_mii_mux[] = {
>> +       AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>> +       AVB_TXD3_MARK,
>> +
>> +       AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>> +       AVB_RXD3_MARK,
>> +
>> +       AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>> +       AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
>> +       AVB_COL_MARK,
>> +};
>
> The MII pin list include RX_ER, but not TX_ER...

    Wikipedia tells me TX_ER is optional for MII.

> ... while the GMII pin list includes both RX_ER and TX_ER. Is that correct?
> Should it be the other way around?
>
> Section "45A.3.13.1 MII Frame Transmission/Reception Timing" of the R-Car Gen2
> datasheet shows timing diagrams for both AVB_TX_ER and AVB_RX_ER, so I'd expect
> both pins to be needed for MII.

    Hm, interesting...

> Unfortunately Section "45A.3.13.2 GMII Frame Reception Timing" shows timing
> diagrams for receive only (thus involving AVB_RX_ER only), so I'm not sure the
> AVB_TX_ER pin is actually needed for GMII.

    It is.

> I don't have schematics for any R-Car Gen2 board that has AVB support, so I
> can't check myself how the MII/GMII is really wired.

    The standard Lager/Porter boards require some modification to use an an 
AVB daughter board, AFAIK.

> Note that this also applies to the existing AVB pinmux data in pfc-r8a7790.c.

    And we haven't really tested MII, only GMII.

[...]

> Gr{oetje,eeting}s,
>
>                          Geert

MBR, Sergei

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Geert Uytterhoeven Dec. 8, 2015, 1:06 p.m. UTC | #3
Hi Sergei,

On Tue, Dec 8, 2015 at 1:30 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 12/8/2015 3:12 PM, Geert Uytterhoeven wrote:
>>> Add the EtherAVB pin groups to the R8A7791 PFC driver.
>>
>> Thanks for your patch!
>>
>>> +static const unsigned int avb_mii_pins[] = {
>>> +       RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
>>> +       RCAR_GP_PIN(5, 21),
>>> +
>>> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
>>> +       RCAR_GP_PIN(5, 3),
>>> +
>>> +       RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
>>> +       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 28),
>>> +       RCAR_GP_PIN(5, 29),
>>> +};
>>> +static const unsigned int avb_mii_mux[] = {
>>> +       AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>> +       AVB_TXD3_MARK,
>>> +
>>> +       AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>> +       AVB_RXD3_MARK,
>>> +
>>> +       AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>> +       AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
>>> +       AVB_COL_MARK,
>>> +};
>>
>> The MII pin list include RX_ER, but not TX_ER...
>
>    Wikipedia tells me TX_ER is optional for MII.

OK. So it may make sense to have a separate pinmux group for it.

BTW, I've just noticed the R-Car Gen2 sh_eth Ethernet (which does 10/100 only)
doesn't have the pin.

>> ... while the GMII pin list includes both RX_ER and TX_ER. Is that
>> correct?
>> Should it be the other way around?
>>
>> Section "45A.3.13.1 MII Frame Transmission/Reception Timing" of the R-Car
>> Gen2
>> datasheet shows timing diagrams for both AVB_TX_ER and AVB_RX_ER, so I'd
>> expect
>> both pins to be needed for MII.
>
>
>    Hm, interesting...
>
>> Unfortunately Section "45A.3.13.2 GMII Frame Reception Timing" shows
>> timing
>> diagrams for receive only (thus involving AVB_RX_ER only), so I'm not sure
>> the
>> AVB_TX_ER pin is actually needed for GMII.
>
>    It is.

OK.

>> I don't have schematics for any R-Car Gen2 board that has AVB support, so
>> I
>> can't check myself how the MII/GMII is really wired.
>
>    The standard Lager/Porter boards require some modification to use an an
> AVB daughter board, AFAIK.

Do you have schematics for those?

>> Note that this also applies to the existing AVB pinmux data in
>> pfc-r8a7790.c.
>
>    And we haven't really tested MII, only GMII.

So I guess the daughterboard uses both RX_ER and TX_ER?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Sergei Shtylyov Dec. 8, 2015, 1:41 p.m. UTC | #4
On 12/08/2015 04:06 PM, Geert Uytterhoeven wrote:

>>>> Add the EtherAVB pin groups to the R8A7791 PFC driver.
>>>
>>> Thanks for your patch!
>>>
>>>> +static const unsigned int avb_mii_pins[] = {
>>>> +       RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
>>>> +       RCAR_GP_PIN(5, 21),
>>>> +
>>>> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
>>>> +       RCAR_GP_PIN(5, 3),
>>>> +
>>>> +       RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
>>>> +       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 28),
>>>> +       RCAR_GP_PIN(5, 29),
>>>> +};
>>>> +static const unsigned int avb_mii_mux[] = {
>>>> +       AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
>>>> +       AVB_TXD3_MARK,
>>>> +
>>>> +       AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
>>>> +       AVB_RXD3_MARK,
>>>> +
>>>> +       AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
>>>> +       AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
>>>> +       AVB_COL_MARK,
>>>> +};
>>>
>>> The MII pin list include RX_ER, but not TX_ER...
>>
>>     Wikipedia tells me TX_ER is optional for MII.
>
> OK. So it may make sense to have a separate pinmux group for it.

    Hm... since this is MAC-to-PHY signal, I'd prefer just adding it to the 
MII group... but you may have a point here.

> BTW, I've just noticed the R-Car Gen2 sh_eth Ethernet (which does 10/100 only)
> doesn't have the pin.

    Th EtherMAC only support RMII which doesn't have this signal at all.

>>> ... while the GMII pin list includes both RX_ER and TX_ER. Is that
>>> correct?
>>> Should it be the other way around?
>>>
>>> Section "45A.3.13.1 MII Frame Transmission/Reception Timing" of the R-Car
>>> Gen2
>>> datasheet shows timing diagrams for both AVB_TX_ER and AVB_RX_ER, so I'd
>>> expect
>>> both pins to be needed for MII.

>>     Hm, interesting...

>>> I don't have schematics for any R-Car Gen2 board that has AVB support, so
>>> I
>>> can't check myself how the MII/GMII is really wired.
>>
>>     The standard Lager/Porter boards require some modification to use an an
>> AVB daughter board, AFAIK.
>
> Do you have schematics for those?

    Daughterboards, you mean? Yes. There are 2 of them, one with Gigabit PHY, 
the other with 100 Mbit one (I don't have that one and haven't tested it).

>>> Note that this also applies to the existing AVB pinmux data in
>>> pfc-r8a7790.c.
>>
>>     And we haven't really tested MII, only GMII.
>
> So I guess the daughterboard uses both RX_ER and TX_ER?

    Yes, for the one with Gigabit PHY and no, for the one with 100 Mbit (that 
one doesn't even seem to have RX_ER connected to anything).

> Gr{oetje,eeting}s,
>
>                          Geert

MBR, Sergei

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Geert Uytterhoeven Dec. 8, 2015, 1:50 p.m. UTC | #5
On Tue, Dec 8, 2015 at 2:41 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>> So I guess the daughterboard uses both RX_ER and TX_ER?
>
>    Yes, for the one with Gigabit PHY and no, for the one with 100 Mbit (that
> one doesn't even seem to have RX_ER connected to anything).

Which means the pin could be used for something else, modulo the fact that
it's part of the avb_mii group, and thus configured for avb...

Thanks for checking!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Patch
diff mbox

Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1740,6 +1740,82 @@  static const unsigned int audio_clkout_m
 	AUDIO_CLKOUT_MARK,
 };
 
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+	RCAR_GP_PIN(5, 14),
+};
+static const unsigned int avb_link_mux[] = {
+	AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+	RCAR_GP_PIN(5, 11),
+};
+static const unsigned int avb_magic_mux[] = {
+	AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+	RCAR_GP_PIN(5, 16),
+};
+static const unsigned int avb_phy_int_mux[] = {
+	AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
+};
+static const unsigned int avb_mdio_mux[] = {
+	AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+	RCAR_GP_PIN(5, 21),
+
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+	RCAR_GP_PIN(5, 3),
+
+	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
+	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 28),
+	RCAR_GP_PIN(5, 29),
+};
+static const unsigned int avb_mii_mux[] = {
+	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+	AVB_TXD3_MARK,
+
+	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+	AVB_RXD3_MARK,
+
+	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
+	AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
+	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
+
+	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
+	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
+	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
+	RCAR_GP_PIN(5, 29),
+};
+static const unsigned int avb_gmii_mux[] = {
+	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+	AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+	AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+	AVB_COL_MARK,
+};
+
 /* - CAN -------------------------------------------------------------------- */
 
 static const unsigned int can0_data_pins[] = {
@@ -4258,6 +4334,12 @@  static const struct sh_pfc_pin_group pin
 	SH_PFC_PIN_GROUP(audio_clk_b_b),
 	SH_PFC_PIN_GROUP(audio_clk_c),
 	SH_PFC_PIN_GROUP(audio_clkout),
+	SH_PFC_PIN_GROUP(avb_link),
+	SH_PFC_PIN_GROUP(avb_magic),
+	SH_PFC_PIN_GROUP(avb_phy_int),
+	SH_PFC_PIN_GROUP(avb_mdio),
+	SH_PFC_PIN_GROUP(avb_mii),
+	SH_PFC_PIN_GROUP(avb_gmii),
 	SH_PFC_PIN_GROUP(can0_data),
 	SH_PFC_PIN_GROUP(can0_data_b),
 	SH_PFC_PIN_GROUP(can0_data_c),
@@ -4597,6 +4679,15 @@  static const char * const audio_clk_grou
 	"audio_clkout",
 };
 
+static const char * const avb_groups[] = {
+	"avb_link",
+	"avb_magic",
+	"avb_phy_int",
+	"avb_mdio",
+	"avb_mii",
+	"avb_gmii",
+};
+
 static const char * const can0_groups[] = {
 	"can0_data",
 	"can0_data_b",
@@ -5081,6 +5172,7 @@  static const char * const vin2_groups[]
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(audio_clk),
+	SH_PFC_FUNCTION(avb),
 	SH_PFC_FUNCTION(can0),
 	SH_PFC_FUNCTION(can1),
 	SH_PFC_FUNCTION(du),